First timer in Verilog with a syntax question

[sassafrassquatch]

Hi!

I hope this is alright for this group. I'm very new to verilog(only a couple days in). I got an Altera DE2 board and want to make pong on a couple led matrices as my first project.

Anyways, Ive been looking through a lot of example code and trying to go through this example: Altera DE2 Project Diglab3

I have most of this example worked out but cant figure out what this code does

oneshot pulser(
.pulse_out(pulse),
.trigger_in(state),
.clk(CLOCK_50)
);



its calling the oneshot function which looks like:


/*The one-shot is a monostable pulser. When the trigger signal goes high,
the output pulse is set high for one clock cycle.
Another output pulse can not occur until the trigger undergoes another positive edge transistion.*/

module oneshot(output reg pulse_out, input trigger_in, input clk);
reg delay;

always @ (posedge clk)
begin
if (trigger_in && !delay) pulse_out <= 1'b1;
else pulse_out <= 1'b0;
delay <= trigger_in;
end
endmodule


the .pulse_out(pulse) notation is what I am unsure about, I've seen that syntax used similarly but cant figure out why.

on that note, here is a pretty decent tutorial I've also been reading:

Welcome To Verilog Page

Once again, if these kind of questions are not allowed here I apologize, otherwise any help is really appreciated.

also, cant seem to wrap code in html for formatting...

 

[bigdogguru]

This is absolutely the correct forum for this question.

However, I'm by no means an expert in Verilog, so give me a little time to research the syntax and run a simulation. I'll get back with you on my findings.

By all means, your welcome to post any relevant links to the threads I've already started. I started this group as a resource point for just such a purpose.

I appreciate your participation.