First time going to make a chip. Need suggestions wherever possible ?

[hcu]

first time going to make a chip . need suggestions whereever possible ???

Hello all,

I posting here a dc_shell script on which we are going to finalize the netlist based on this. we dont do the backend so we are relying on someothers comp. so our job is netlist signoff.

reports shows there is no setup issues but got hold violations and we relying on backend to fix those. other power numbers and area numbers are ok and as expected. target frequency is 600 Mhz.

Is there anything else missing in the script or any advice or suggestions. please go through the script .

# ********************************************************************************************************** //
#
# 	This is DC script for synthesising MD_DB using slowslow library
# 	Operating conditions 	:  SS0p81v125c
#	Operating frequency  	:  $CLK_PERIOD
# 	Target Technology	:  TSMC 28nm HPC+ 
# 	Tool versions		:  Design compiler L-2016.03-SP5-7
#	Engineer		:  Hardware Team
#
# ********************************************************************************************************** //

# To remove previous loaded designs if any
remove_design -all
set_app_var suppress_errors {DDB-74 VER-130 VER-318}



# Reading Standard cell Library
set TARGET_LIBRARY_FILES          "/home/synopsys/TSMC_LIB/28nmHPCPLUS/tplusbwp12t30p140ssg0p81v0c.db"
set target_library $TARGET_LIBRARY_FILES
# Reading SRAM cell Library
set SRAM_LIBRARY_FILES1   "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/thvtb32x32m4sw_ssg0p81v0c.db" 
set SRAM_LIBRARY_FILES2   "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/thvtb128x32m4sw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES3   "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/thvtb256x32m4sw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES4	  "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/thvtb512x32m4sw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES5	  "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/thvtb1024x32m4sw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES6	  "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/thvtb4096x32m4sw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES7	  "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/thvtb16384x32m8sw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES8   "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/thvtb32768x32m16sw_ssg0p81v0c.db"

set SRAM_LIBRARY_FILES9   "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/thvtb2048x32m4sw_ssg0p81v0c.db"  
set SRAM_LIBRARY_FILES10  "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/tuhdb32x32m4mw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES11  "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/tuhdb64x32m4mw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES12  "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/tuhdb128x32m4mw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES13  "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/tuhdb512x32m4mw_ssg0p81v0c.db"
set SRAM_LIBRARY_FILES14  "/home/synopsys/SRAM_LIBS/SSG_0P81V_0C/tuhdb2048x32m4mw_ssg0p81v0c.db"  
  								   
# Reading SROM cell Library				           
set SROM_LIBRARY_FILES1   "/home/synopsys/SROM_LIBS/t1024x32m8m_ssg0p81v0c.db"
# Reading IO PAD Library
set IOPAD_LIBRARy_FILES1  "/home/synopsys/IOPAD_LIBS/tpgv18ssg0p81v1p62v0c.db"

# Synthetic_library path for designware components
set synthetic_library "/home/synopsys/syn/L-2016.03-SP5-7/libraries/syn/dw_foundation.sldb"

set dcSnpsRoot "/home/synopsys/syn/L-2016.03-SP5-7"
 

set search_path 	"/home/NET_LIST_RELEASE/SOC_4_compile_ROM_DC $dcSnpsRoot/libraries/syn $dcSnpsRoot/minpower/syn $dcSnpsRoot/dw/syn_ver $dcSnpsRoot/dw/sim_ver /home/synopsys/TSMC_LIB/28nmHPCPLUS/"

set link_library "* $target_library $SRAM_LIBRARY_FILES1 $SRAM_LIBRARY_FILES2 $SRAM_LIBRARY_FILES3 $SRAM_LIBRARY_FILES4 $SRAM_LIBRARY_FILES5 $SRAM_LIBRARY_FILES6 $SRAM_LIBRARY_FILES7 $SRAM_LIBRARY_FILES8 $SRAM_LIBRARY_FILES9 $SRAM_LIBRARY_FILES10 $SRAM_LIBRARY_FILES11 $synthetic_library $SRAM_LIBRARY_FILES12 $SRAM_LIBRARY_FILES13 $SRAM_LIBRARY_FILES14 $SROM_LIBRARY_FILES1 $IOPAD_LIBRARy_FILES1"

set DESIGN_NAME                   "SOC_DB_V3"

set CLK_PERIOD			  "1.25"
set CLK_PERIOD1			  "5"

set RESULTS_DIR			  "RESULTS_0.81v0"
set REPORTS_DIR			  "REPORTS_0.81v0"
# *************************************************************************
# 			  Reading source files  
# *************************************************************************
source read_source.tcl



# *************** Setting top module as current design ********************
current_design {MD_DB_IO_TOP}  
# ************** Linking current design to libraries **********************
link

# Operating conditions
set_operating_conditions ssg0p81v0c -library tbwp12t30p140ssg0p81v0c
set_drive [expr 0.288001] [all_inputs]
set_load [expr 0.06132] [all_outputs]

# *************************************************************************
#   				Clock generation
# *************************************************************************
# PAD clocks  20 MHz
create_clock   -name "Ref_Clock_XIN_pad"        -period 50 [get_ports Ref_Clock_XIN_pad]
# PAD clocks  100 MHz
create_clock   -name "PLLOUT"        -period 1.25  [get_ports PLLOUT]


# Host clk clk 200 MHZ
create_clock    [get_pins MD_DB_without_pads/MD_host_top_instance/clk]  -name host_clk  -period 5  
# Peripherals  100 MHz
create_clock   [get_pins MD_DB_without_pads/apb_peripherals/PCLK_pclk]  -name PCLK_pclk  -period 10  
# ADC   20MHz
create_clock   [get_pins MD_DB_without_pads/slave_instance/C_CLK]  -name C_CLK  -period 50  
# Clock out
create_clock   [get_pins MD_DB_without_pads/clk_div_uut3/clk_div_clk_out]  -name PCLK3  -period 12  -waveform {0 6}
# Asynchronous clk  to I2C
create_clock   [get_pins MD_DB_without_pads/clk_div_uut1/clk_div_clk_out]  -name PCLK1  -period 12  -waveform {0 6}
#


# Set input delay and output_delay are  Used  with set_load and set_driving_cell,
set_input_delay  0.15 -clock Ref_Clock_XIN_pad  [all_inputs]
set_output_delay 0.15 -clock Ref_Clock_XIN_pad  [all_outputs]

#set_switching_activity -toggle_rate 0.20 -base_clock S_AXI_ACLK -static_probability 0.015 -type inputs  ## GETTING ERROT no licence for power optimization

#opt-1206
set compile_seqmap_propagate_constants false 
set compile_delete_unloaded_sequential_cells false
#opt-1055
set ungroup_keep_original_design true 
#set compile_seqmap_enable_output_inversion false #opt-1208
# opt-1215
set compile_enable_register_merging false 

compile_ultra -no_autoungroup 
#-no_seq_output_inversion

file mkdir ${DESIGN_NAME}/${RESULTS_DIR}
file mkdir ${DESIGN_NAME}/${REPORTS_DIR}
#########################
#   Writing Results	#
#########################
write_file -hierarchy -format verilog -output ${DESIGN_NAME}/${RESULTS_DIR}/${DESIGN_NAME}_gates_${CLK_PERIOD}ns.v
write_file -f ddc -o ${DESIGN_NAME}/${RESULTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}ns.ddc
write_link -nosplit -out ${DESIGN_NAME}/${RESULTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}ns.link
write_sdf   ${DESIGN_NAME}/${RESULTS_DIR}/${DESIGN_NAME}.sdf
write_sdc   ${DESIGN_NAME}/${RESULTS_DIR}/${DESIGN_NAME}.sdc
##########################
#    Writing Reports     #
##########################
report_qor  >  ${DESIGN_NAME}/${REPORTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}_qor.rpt
report_area >  ${DESIGN_NAME}/${REPORTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}_area.rpt
report_power -hierarchy >  ${DESIGN_NAME}/${REPORTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}_power_h.rpt
report_area -hierarchy >  ${DESIGN_NAME}/${REPORTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}_area_h.rpt
report_cell >  ${DESIGN_NAME}/${REPORTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}_cell.rpt
report_power -nosplit > ${DESIGN_NAME}/${REPORTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}_power.rpt
report_timing >   ${DESIGN_NAME}/${REPORTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}_timing.rpt
report_synthetic  > ${DESIGN_NAME}/${REPORTS_DIR}/${DESIGN_NAME}_${CLK_PERIOD}_synthetic.rpt

regards,

hcu

 

[ThisIsNotSam]

Re: first time going to make a chip . need suggestions whereever possible ???

I don't see any step adding tiehi/tielo cells, but maybe you want to do that later at physical synthesis.
I see that you are doing synthesis with the IO library included, that is not always wise. Depends.
I see no max_tran settings, which could be ok or could make physical synthesis work much much harder. Hard to say, at 600MHz it should be fine.
I see no ideal nets being set, but I don't know your design to tell if there are any other than rst/clk.
I see no set_dont_use statements, which means synthesis could be using hold fix cells already (bad idea!), some flop types that you don't want, some padded version of special cells, etc., all those things that you may need to avoid depending on the std cell library you are using.

I see several clock domains but no false paths between them. No explicit synchronization anywhere. Not sure how you are handling CDC. Could be fine, could be all wrong. Impossible to tell from the script.

 

[Spoorthi_Harithas]

Re: first time going to make a chip . need suggestions whereever possible ???

Why have you not defined clock groups? I would suggest you to revisit synthesis constraints once.

Also now you have synthesis script templates from Synopsys/Cadence sites. You can download them and modify accordingly as per your design.

I hope this helps you