radialmind
Newbie level 2
Hello,
I'm a programmer by trade in C. A hobby of mine since 2 years is working with FPGA's, so I'm relatively new to this and never got any formal training or background using them. So it's purely my own interest.
My current project is an attempt to create a DVB-S modulator. I have a PC that I can connect to the FPGA experiment board through which I can send the MPEG packets. My intention is just to get the error coding and modulation right. I've got Reed Solomon, PRBS, convolutional encoding and inner coding working. Most of that work involves straight-forward logic though.
The specification and my interpretation becomes a bit hazy after the inner coder, so please assert the following for correctness. I'm following a document from d-atv.com where they describe how they implemented their modulator on the FPGA. The first part is a FIR filter, followed by an upsampling process and a CIC comb filter to finish things off. I'm slightly stuck at the FIR filter for now. I managed to design a FIR filter candidate using the fdatool in matlab, so I have the coefficients for the implementation. If my understanding from the DVB-S spec is correct, I should have two bitstreams X and Y after the inner coder, which according to the d-atv implementation are each fed into a FIR filter. This bitstream for both channels is 1 bit wide in my implementation, so either '0' or '1'.
My doubts are how to apply these X/Y bitstreams.
1. The generated FIR filter implementation from matlab implies a float input and output and real coefficients with the use of a multiplier. Since I have a 1-bit input, I thought I could use that as a selector for the coefficients to prevent the use of a multiplier. My idea is thus to pre-multiply the coefficient with numbers from a suitable bit-width, then add the positive or negative version depending on a 0 or 1 in the X/Y signal. All these selected coefficients are then added together to produce the final I/Q output.
2. From what I can gather, the signal as is should be inserted into the FIR filter for processing. The paper mentions something like a 4-times upsampling as well though, so I'm not sure if the filter works on an upsampled signal being shifted into the filter or whether it uses the signal as is.
Your help is appreciated.
I'm a programmer by trade in C. A hobby of mine since 2 years is working with FPGA's, so I'm relatively new to this and never got any formal training or background using them. So it's purely my own interest.
My current project is an attempt to create a DVB-S modulator. I have a PC that I can connect to the FPGA experiment board through which I can send the MPEG packets. My intention is just to get the error coding and modulation right. I've got Reed Solomon, PRBS, convolutional encoding and inner coding working. Most of that work involves straight-forward logic though.
The specification and my interpretation becomes a bit hazy after the inner coder, so please assert the following for correctness. I'm following a document from d-atv.com where they describe how they implemented their modulator on the FPGA. The first part is a FIR filter, followed by an upsampling process and a CIC comb filter to finish things off. I'm slightly stuck at the FIR filter for now. I managed to design a FIR filter candidate using the fdatool in matlab, so I have the coefficients for the implementation. If my understanding from the DVB-S spec is correct, I should have two bitstreams X and Y after the inner coder, which according to the d-atv implementation are each fed into a FIR filter. This bitstream for both channels is 1 bit wide in my implementation, so either '0' or '1'.
My doubts are how to apply these X/Y bitstreams.
1. The generated FIR filter implementation from matlab implies a float input and output and real coefficients with the use of a multiplier. Since I have a 1-bit input, I thought I could use that as a selector for the coefficients to prevent the use of a multiplier. My idea is thus to pre-multiply the coefficient with numbers from a suitable bit-width, then add the positive or negative version depending on a 0 or 1 in the X/Y signal. All these selected coefficients are then added together to produce the final I/Q output.
2. From what I can gather, the signal as is should be inserted into the FIR filter for processing. The paper mentions something like a 4-times upsampling as well though, so I'm not sure if the filter works on an upsampled signal being shifted into the filter or whether it uses the signal as is.
Your help is appreciated.