FIR filter IPCore need 12 bit in out

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Hi;
i have a signal in 40 mhz IF and down-converted it by 12.5 mhz sampler so i have my interested 3 mhz bandwidth in base band.

Now:
i need to filter unwanted harmonics buy using a lo pas filter with 7 taps and 5 mhz stop band.

Problem:
i have ADC in 12.5 Mhz and 12 bit accuracy i need 12 bit output from it.
In the IP Core when i put 12 bit as input and 12 bit as output ( in truncate LSB mode) when it is generated the codes input requires 15 bit ( we said 12 bit to it) and also the output 12 bit too.

what is your solutions?
 

Hi,

It is not unusual, that a FIR filter internally needs a larger bit width than input and output.

Klaus
 

So What can i do? do you have any solution to be able to filter a 12 bit data and get a 12 bit data in its output?
 

What's your problem? Use an internal filter word width as required and cut result LSBs according to the intended output resolution.
 

my input is 12 bit and i am able just to pickup 12 MSB bits from its output !!!

it may show Distortions and or be saturate all the time !!!

What is your proposition if you had 12 bit input?

i can give 8 bit MSB in input and get 12 bit in output but is its output signal good ?( without distortion) ?
 

Hi,

It's just the opposite.
A FIR filter works with multiplying and adding.
Imagine 12 bit x 12 bit multiplier, it has a dynamic output range of 24 bits. If you truncate msbs you may cause saturation or reversing the output causing large distortions. If you truncate lsbs you will loose resolution.

FIR filters may cause amplification at some frequencies, therefore you need headroom in the MSBs.
FIR filters may cause attenuation at some frequencies, Therfore - not to loose resolution - you need headroom at the LSBs.

So even 15 bits surely is a compromise.

Trust your compiler and see what happens.

Klaus
 

problem is that :
when you trying to have a FIR filter with more than 7 taps, and 12 bit as input and 16 as output , the Core generates you a filter that needs 16 bits as in put and 16 bit as output.

coregen dos note design as i want from it!

please check it out in your compiler and say what you see !
 
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Hi,

Where is the problem to connect a 12 bit output to a 16 bit input und setting the four unused input signals to "0"?

The same is with the outputs. Just use the 12 you need.

Klaus
 

KlausST said:
Hi,

Where is the problem to connect a 12 bit output to a 16 bit input und setting the four unused input signals to "0"?

The same is with the outputs. Just use the 12 you need.

Klaus
Click to expand...



this is how i config my core


as you see when i was designed the FIR core i asked to generate 12 bit input and 16 bit output BUT Core generated a core that ask me to to supply it with 16 bit input bits and it gives 16 bit Output bits!

Why it changes 12 to 16 automatically ?
 

Why it changes 12 to 16 automatically ?
Click to expand...
Not obvious at first sight, may be a bug or known behaviour. You could ask Xilinx support, if it's really a problem.

I believe however that the suggestion by KlausST completely solves the issue for the time being.
 

Scaling of coefficients in powers of 2, and saving final multiply or divide at the end is the most efficient way to implement in many cases. Coregen may be designed to take this into account. If you don't need all 16 input bits, just don't use them! Optimization will try to reduce the logic footprint where it can. But, keeping some things internally in 16bits gives you the dynamic range you may need and reduces the CLBs used for doing multiplies
 

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