Finite state machine VS rising edge

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uart is
    Port ( CLK : in  STD_LOGIC;
           EN : in  STD_LOGIC;
           tx : out  STD_LOGIC);
end uart;

architecture Behavioral of uart is

type state is (idle, start, d0, d1, d2, d3, d4, d5, d6, d7, stop);

signal curr_s, next_s : state;

constant data : STD_LOGIC_VECTOR (7 downto 0) := "00111100";

begin

state_proc : process(CLK)
begin
    if (rising_edge(CLK)) then
        curr_s <= next_s;
    end if;
end process;

fsm_proc : process(curr_s, EN)
begin
    case curr_s is
        when idle  => tx      <= '1';
                        if (rising_edge(EN)) then --THAT IS THE PROBLEM
                            next_s <= start;
                        else
                            next_s <= idle;
                        end if;
        when start =>  tx      <= '0';
                            next_s <= d0;
        when d0      =>  tx      <= data(0);
                            next_s <= d1;
        when d1      =>  tx      <= data(1);
                            next_s <= d2;
        when d2      =>  tx      <= data(2);
                            next_s <= d3;
        when d3      =>  tx      <= data(3);
                            next_s <= d4;
        when d4      =>  tx      <= data(4);
                            next_s <= d5;
        when d5      =>  tx      <= data(5);
                            next_s <= d6;
        when d6      =>  tx      <= data(6);
                            next_s <= d7;
        when d7      =>  tx      <= data(7);
                            next_s <= stop;
        when others=>  tx      <= '1';
                            next_s <= idle;
    end case;
end process;
end Behavioral;

reg EN_reg;

process (CLK, EN)
begin
  if(rising_edge(CLK))
  begin
    EN_reg<=EN;
  if(EN='1' and EN_reg='0')then
    //do whaterver you need here to change state
   end if
  end
end process