fingers and multipliers

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yaasi

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what is the difference between the transistor fingering and multiplication?
 

Yassi:

From my knowledge Fingers means cutting the total width in to fingers.
i.e W=20u, L=2u. Now if we finger that one to 5 fingers, parameters are like W=4u, L=2u, fingers=5.

Multiplication: To have the same transitor in number of times.

i.e. you have one transitor W=5u, L=2u, Fingers=3, Multiplication=4.
That means you have 4 bunches fo 3 fingered transistors with w=5u, l=2u for each finger.
I guess it is correct. But I need conformation. Bcoz this thing you will see in Virtuso schematic editor. Ingeneral we will use View logic for schematics. That's why I am not sure about this. Comments are welcome.
 

I also want to learn about it.
For me it makes no differenceo(∩_∩)o...
 

For simulation, if you use multipliers in the schematic then the full drain and source area will be given in the netlist. If you use fingers then it should calculate the reduced source/drain area for the simulation.
However, fingering the MOS will give you less parasitic resistance.
 

The finger transistors can use the S/D node.
And the multipliers are signle transistors with themsleve's S/D.
You should layout the finger transisitor and multipliers,and you will know all.
 

Let us consider we have one transitor of W=5u, L=2u, Fingers=3, Multiplication=4.
That means you have 4 bunches fo 3 fingered transistors with w=5u, l=2u for each finger.

If a transistor has 3 fingers then it means that its either S or D are merged and we will connect the rest rite.

If we consider the multiplier there also we connect all the S together and D together.

I could not get it properly how are they different?
Any how the total width=w * f * m (w-width,f-fingers,m-multipliers)....
 

Yassi:

That's what I told earlier. In this topic I am little bit poor. Let's wait if some one gives comment on this. Sorry for making you confused.
 

We can say they are functionally same.
But you must make sure the layout and sche. are same, otherwise it cannot pass the LVS check.
Acctually, the area consumed are different, because multiple fingers transistor can share their diffusion area to be either source or drain.

 

multipliers ; separate transistors connected in parallel

fingers ; parallel transistors share diffusion ; i.e. one drain or source diffusion shared between 2 transistors , and so , this decrease the parasitic capacitance
 
how we decide the maximum && minimun numbers of finger in layout
 

Sometime I use divide one MOS to two for matching. But if it don't need match, fingering will be better for layout.

But for RF design, fingering is better for reduce parasitic capacitor.

but for simulation, there will nor different.
 
From the "definition" point of view, THEY ARE EXACTLY THE SAME. They are two different ways to talk about parallel mos transistors.

The difference is how the PCELL (parametrized cell) is giving you the transistor in one and other case...

- FINGERS: It'll give you a unique cell with the complete transistor with all the fingers. Usefull when you want a cell as compact as possible.

- MULTIPLICITY: It'll give you as much transistors as the multiplicity indicates. Usefull when you want to split the transistor to make some interdigitation or crosscoupling matching technique.

To recap, THIS IS EXACTLY THE SAME AND THE BETTER ONE DEPENDS ON WHAT'S YOUR NEED WITH THE TRANSISTOR...
 
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    Andreew

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    bhu_sub

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fingers =folds
multiplier =unit width multiplied by the multiplier

fold is used to reduce the source/drain diffusion.
multiple commonly used in current mirrors when making multiple bias currents
 

finger usually common diffusion while multiplied usually separated diffusion.
 

by using FINGERING parasitic resistance will reduce, ok.
but what about PARASITIC CAPACITANCE. i think it will increase becoz, C gs , C gd , Cgb will increase.

is it correct, pls comment.
 

No...actually fingering reduces parasitic resistance and capacitance. It reduces parasitic capacitance by reducing the overall drain/source area and perimeter. Quantitatively, drain/source capacitance reduces by about half when you finger a MOS device by more than 4-5. Actually it also reduces the threshold voltage by a small amount in deep submicron technologies.
 



that's right.
 

Simulation will be nearly same for old process(>=0.5um). But it will be lead to big difference for deep submicron process (<=0.35um). Usually 0.35um and below process will support models for finger.
 

m=multiplier
nf = mfactor

total size of transistor is m * nf * (w/l)
if the transistor size is 8*(2/1)
we can split it as 1*8*(2/1) or 4*2*(2/1)
The first one has better LOD and should be prefered.
Hope this helps.
 
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