Finfet stacked devices current mirror

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Giemme

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Hi all,
I'm starting approaching analog design using Finfet technology, and I'm confused about definition of the common saturation margine when using stacked devices.
Suppose I''m designing a simple current mirror, and I use stacked devices since I've not choice of L but Lmin; in a stacked devices configuration, what are the vgs, vds, vdsat etc to be considered to define the bias point? Since only the device on top of stack Is in saturation, make sense to assume It as a degenerated device and consider that its vdsat Is what matter?

Thanks!
 

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It may be a mistake to be too analytical, or try to follow methods for longer, more "classical" devices.

I've observed up close, some analog "portable library" folks try to do finFET versions and what I saw, as an analog guy, disgusted me. Talking sub-40dB AVOL (typ) and other ugliness.

You 'll be forced to do the kinds of things you're looking at, and away from "just one cascode layer, same old" to "oh, crap, I need 3 to make Rout useful and that makes two of 'em "live" rather than DC-fixed...".
 

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I'm not sure I've well understood...but seems your message sounds like "don't necessary look to old-fashioned metrics, but rely more on your final parameters of interest"...isn't it?
 

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The amplifier "metrics" are the applications' demand to you. They want what they want, for the price agreed upon.

The sausage-making machinery is way different and expect some things aren't achievable no matter how many fragile and nonlinear baby transistors you throw at the job.

Baby transistors' Rout is poor and highly varying vs Vds. Id-Vds I've seen say impact ionization is there well before Vds(max), the qualities of long channel saturation your "method" design approach is after are long gone. The math doesn't represent and oh, yeah... impact ionization is hot carriers is why you get to do aging as a design corner to live with. Sweet, huh?
 

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