[SOLVED] Finfet based inverter netlist

[VirtuosoDracula]

Hello,

I created an inverter netlist using finfet models, in which I mentioned 'fpitch' 'nfin' 'nf' instead of the the width.

Much to my surprise, I didn't get the correct results; but with the same netlist if I replace the finfet parameters with a width, I get the correct results.

Any suggestions,what I might be missing here?

Thanks in advance!
VD

 

[erikl]

Where - i.e. from which tool - didn't you get correct results? Simulation, layout creation, or Dracula LVS? May be the used tool doesn't (yet) know - or cannot assign - these Finfet parameters.

 

[VirtuosoDracula]

Hi erikl,

Yes it was during the spice simulation that I didnt get the correct results, but that was due to the goof up I did with the order of the ports I provided in the subckt definition and its instantiaition. The problem has been resolved now.

 

[ranger01]

Hi VD,

Could you please share the inverter netlist, you used with this experiment ? Thanks for your time. I am trying to simulate a FinFET based inverter in hspice using PTM-16nm model