`timescale 1ns / 1ps
module freq_counter( input clk_100mhz,
input reset,
input low_freq_clk,
output reg [13:0] out1
);
reg low_freq_clk_x, low_freq_clk_xx, low_freq_clk_xxx;
reg [25:0] lo_counter;
reg [26:0] hi_counter;
always @(posedge clk_100mhz or posedge reset) begin
if (reset) begin
lo_counter <= 26'd0;
hi_counter <= 27'd0;
out1 <= 14'd0;
end
else begin
low_freq_clk_xxx <= low_freq_clk_xx;
low_freq_clk_xx <= low_freq_clk_x;
low_freq_clk_x <= low_freq_clk;
if (low_freq_clk_xxx & ~low_freq_clk_xx) lo_counter <= lo_counter + 1'b1;
// Output total frequency when one second is up
if (hi_counter == 27'd100000000) begin
out1 <= lo_counter;
lo_counter <= 1'b0;
hi_counter <= 1'b0;
end else
hi_counter <= hi_counter + 1'b1; // Elapse time
end
end
endmodule