finding registers in synthesized gate level netlist with verilog VPI or PLI

[tariq786]

I am trying to write a free opensource PLI/VPI routine that will extract the registers from synthesized gate level netlist along with the associated clock.

Lets look at a synthesized gate level code snippet below

DFQD1 \out_reg[28] ( .D(N41), .CP(clk), .Q(out[28]) );
DFQD1 \out_reg[27] ( .D(N40), .CP(clk), .Q(out[27]) );
DFQD1 \out_reg[26] ( .D(N39), .CP(clk), .Q(out[26]) );
DFQD1 \out_reg[25] ( .D(N38), .CP(clk), .Q(out[25]) );


What i am interested in is finding the hierarchical name of clock and Q output of all such registers in a design. So the output should be as follows

test.uut.u0.\out_reg[28].out[28]
test.uut.u0.\out_reg[28].clk

test.uut.u0.\out_reg[28].Q
test.uut.u0.\out_reg[28].CP

Note i am showing both high and low connections.

Note merely finding registers is not the goal. I am interested in finding register and the associated clock. In a multiple clock domain design or design with CDC (Clock Domain Crossing), merely finding registers is not sufficient, we also need the associated clock.

If you know some other approach for gate level design, please share it with me.

Again, when this is complete, it will be submitted to the sourceforge.net with all the source code.

Thanks

Kind Regards,

 

[yx.yang]

I suppose you want to done this under DC or PT (And PT is better). If that's true, I think you can make it.
You just need extrac some "attribute" of the design from PT and maybe some "attribute" from the cell library and some command in PT.
So you may need to man the "get_attribute" / "list_attribute" command in PT.

For example: find out the hierarchy of all DFFs, you may use the command like: get_cells -hierarchy -filter "is_sequential == true". //Note: this may also find out RAMs
Then, you may need use a PT command to change the "object" data format in PT to text data format, which you can print in a file. //Note: the return value of "get_cell" function is PT defined "object" data format, this can't be used in TCL directly. PT provide a comamnd to change "object" to simple TCL data format, but I forget that command.

 

[sam536]

If you are using PT , its 2 line command.

set regs [all_regs] ; which will take all registers into regs variable.
foreach_in_coll reg $all_regs {
}

your code need to extract the register name , Q pin and clock. Use the attributes command to find all the required information. use report_attr -all. or list_attr in PT to find the supporting attributes in the current versions.

Regards,
Sam