[SOLVED] Finding path from Primary Inputs to a net in Design Compiler or PrimeTime

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anandhavel

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Hi,
If I specify a net in a verilog module, is it possible to find the primary inputs and path to the specified nets in either PrimeTime or DesignCompiler?

Thanks,
Anand
 

try all connected to that net and then fanin / all_fanin
Not sure of the exact command been a while since i used DC
 
Thanks for the help englishdogg.

I found that "report_transitive_fanin" works.
 

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