Finding an IP Power Analysis Tool

[luoyanghero]

After designing an IP, you need to estimate the area, maximum frequency, and power consumption.
As for the IP design level: the area can be estimated using the nand numbers; the highest frequency, given the process library, run the estimation using design compiler tool.
But for power consumption, is there some good software for power analysis?
I know that SpyGlass can do power analysis, PrimeTime can do power calculation, Joules can do power calculation.
What are the characteristics of these three tools?
Is there corresponding training document or project about the 3 tools to share?

 

[luoyanghero]

Rtl, waveform file, and foundry library file are required to analyze power consumption with spyglass.
For IP designers, rtl and waveform files are available, but foundry library may not be available, which is not convenient for analysis.
Is there a tool that only needs rtl and waveform files to analyze power distribution?

 

[ThisIsNotSam]

Rtl, waveform file, and foundry library file are required to analyze power consumption with spyglass.
For IP designers, rtl and waveform files are available, but foundry library may not be available, which is not convenient for analysis.
Is there a tool that only needs rtl and waveform files to analyze power distribution?

any synthesis tool will do this for you. try genus or dc.

 

[uditkumar1983]

Power analysis can be done at various stage of design flow. Additional information help in accurate power estimation

1. At RTL level
Any tool doing RTL power estimation, takes following input
a. RTL (Mandatory)
b. Simulation waveform(s) representing the practical design scenario (This is optional input but if available provide more accuracy, In absence of this information tool try to estimate activity on various design signals).
c. Technology library: Mandatory, This is required for map RTL into cells. Some tools have default library for synthesis purpose, but it is always recommended to use the technology library aligned to IP synthesis.

2. Netlist level
a. Netlist (Mandatory)
b. Simulation waveform(s) representing the practical design scenario (This is optional input but if available provide more accuracy, In absence of this information tool try to estimate activity on various design signals).
c. parasitic information for calculation of actual delays.

The netlist level power estimation can be just after the synthesis or after complete PNR.