Find the gate capacitance per um

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ccw27

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Does anyone know the gate capacitance per µm of both 1.5V NMOS and PMOS in UMC 0.15 process? I can't seem to find in the technology design manual.

Thanks
 

Is the model is BISM3?
If yeath, you can refer to the relation BISM3 parameter and the UMC 0.15 process model.

and another way is to get it by the UMC .15 process engineer.
 

Yea the model is BSIM3. Can you elaborate more?

Thanks
 

You can check it in the spice model file
 

run simulation and find the cap in .lis file
 

Theoritically, you can get the following parameters from your BSIM 3v3 model files.

tox ( which is the thickness of oxide) m
Cov - the over lap capacitance. F/m

From tox, you can calculate the Cox by Cox = eps0 * epsSi/tox
where esp0 - permitivity of free space = 8.8e -14 F/cm
espsSi - Dielectric constant of SiO2.

Then you can get the whole gate cap as per the region of operation.

But the best method would be to run a simulation and check in the .lis file. This solves the problem of calculating and this is more accurate
 

where is .lis file located? I am using Cadence spectre

Thanks
 

If you are using SPECTRE from Analog Artist/Affirma, you can open the Results----> Print------> DC operating Points and then select the transistor you want to measure the gate capacitance. Or else, if you are running spectre from Console, you can go to the element.info file or dcOp.dc file and open it in the results browser
 

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