Good, then at least we are talking about roughly the same thing.
Dunno, some parts of your problem description are too vague to know for sure. (*) What I can say for certain is that I have solved it in practice in the way I described it.
(*)Yes yes,
you may think you have stated things clearly. Judging by the replies in this thread several people beg to differ. Me included.
Anyways, you can use something along these lines.
| Code Verilog - [expand] |
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| module fix_complex_problem_of_16in_8out(
input clock,
input [15:0] din,
output reg [7:0] dout
);
reg byte_sel = 0;
always @(posedge clock) begin
byte_sel <= ~byte_sel;
dout <= (byte_sel) ? din[15:8] : din[7:0]; // THIS MUX. This one. This right here is a 2-to-1 MUX. For context, see below. :P
end
endmodule
// ... and then you instantiate this like so
wire [7:0] new_spiffy_1_byte_result_that_your_following_processing_can_use;
fix_complex_problem_of_16in_8out fix_complex_problem_of_16in_8out (
.clock (your_fifo_READ_clock),
.din (your_aabb_16_bit_data_OUTPUT_from_your_fifo),
.dout (new_spiffy_1_byte_result_that_your_following_processing_can_use)
);
// And then feed this 8-bit "new_spiffy_1_byte_result_that_your_following_processing_can_use" signal to
// whatever processing you need. |
Obviously there is work required on your part. I only give you some idea on you could approach things. One thing I conveniently and happily ignored due to lack of details provided, is things like fifo being empty/full/whatever. But since you know the specifics of your fifo I am sure you can incorporate that. If you need another MSB/LSB order then you can just change the MUX. What MUX you ask? I'll retro-actively mark it in the code up there.
What you still have to do yourself is read from the fifo on only the even cycles. I'd give you some code for it, but lack of details of your fifo enables my laziness.
Good luck!