[SOLVED] fifo implementation using a counter

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sandy3129

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hai every one , my question is , normally in a fifo we write into the fifo and then read it from the fifo in the next cycle, so datacount will be '1', but what if i want to write 5 data serially and then read it from fifo , i want dataout to be read as 5 bunches at a time . here is my code


Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_misc.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
 
 
entity danger1 is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           dataout : out  STD_LOGIC_vector(31 downto 0);
       a: out  STD_LOGIC;
       b : out  STD_LOGIC;
           full:out  std_logic;
           almost_full: out std_logic;
           empty : out std_logic;
           almost_empty: out std_logic;
       data_count: out  STD_LOGIC_vector(10 downto 0);
       prog_full: out std_logic;
       prog_empty: out std_logic
              );
end danger1;
 
architecture Behavioral of danger1 is
 
signal dout : std_logic_vector(31 downto 0 );
signal count : std_logic_vector(31 downto 0 );
signal din : std_logic_vector(31 downto 0 );
signal wr_en : std_logic;
signal rd_en : std_logic;
type state_type is (rst1,write1,read1);
signal state : state_type;
 
 
 
 
component fifo_generator_v6_2
    port (
    clk: in std_logic;
    rst: in std_logic;
    din: in std_logic_vector(31 downto 0);
    wr_en: in std_logic;
    rd_en: in std_logic;
    dout: out std_logic_vector(31 downto 0);
    full: out std_logic;
    almost_full: out std_logic;
    empty: out std_logic;
    almost_empty: out std_logic;
    data_count: out std_logic_vector(10 downto 0);
    prog_full: out std_logic;
    prog_empty: out std_logic);
end component;
 
 
begin
a<=wr_en;
b<=rd_en;
process(clk,reset)
  begin
  
    if(clk'event and clk='1') then
      if(reset ='1') then
        count <= (others=>'0');
      elsif(wr_en= '1') then
        count<= count + 1;
        end if;
     end if;
end process;
 
 
process(clk)
begin
if(clk'event and clk='1') then
   if (reset='1') then
     wr_en<= '0';
     rd_en<='0';
     state<= write1;
      else
         case (state) is 
    
                when rst1=>
                       wr_en<= '0';
                  rd_en<='0';
                     state<=write1;
        
                  when write1=>
                          wr_en<='1';
                             rd_en<='0';                             
                            state<=read1;
                        
          when read1=>
                                 
                        wr_en<='0';
                            rd_en<='1';                             
                            state<=rst1;
                                    
         end case;
      end if;
end if; 
end process;
 
U0 : fifo_generator_v6_2
        port map (
            clk => clk,
            rst => reset,
            din => count,
            wr_en => wr_en,
            rd_en => rd_en,
            dout => dataout,
            full => full,
            almost_full => almost_full,
            empty => empty,
            almost_empty => almost_empty,
            data_count => data_count,
            prog_full => prog_full,
            prog_empty => prog_empty);
        
 
end Behavioral;
 
Last edited by a moderator:

1.Increase width of read data from 32 to 32*5.
2.Stay in write1 state for 5 cycles and then go to read1 state.
3.Regenerate the FIFO having respective write and read widths.
 
how to increase read width data???

staying in write state for 5 cycles means is it like this 


Code VHDL - [expand]
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process(clk)
begin
if(clk'event and clk='1') then
   if (reset='1') then
     wr_en<= '0';
     rd_en<='0';
     state<= write1;
      else
         case (state) is 
    
                when rst1=>
                     wr_en<= '0';
                     rd_en<='0';
                     state<=write1;
        
                   when write1=>
                     wr_en<='1';
                                          rd_en<='0';                             
                                         state<=write2;
                                     
              when write2=>
                          wr_en<='1';
                                      rd_en<='0';                             
                                      state<=write3;
            when write3=>
                          wr_en<='1';
                                       rd_en<='0';                             
                                      state<=write4;
            when write4=>
                          wr_en<='1';
                                        rd_en<='0';                             
                                      state<=write5;
            when write5=>
                           wr_en<='1';
                                        rd_en<='0';                             
                                        state<=read1;
                        
             when read1=>
                         wr_en<='0';
                     rd_en<='1';                             
                            state<=rst1;
                                    
         end case;
      end if;
end if; 
end process;
 
Last edited by a moderator:

I fear the problem is still poorly specified. What does "read as 5 bunches at a time" exactly mean? Read in one clock cycle?

In the latter case, you need a FIFO with different read and write data widths, a feature that is probably unsupported in standard SCFIFO or DCFIFO IP. So you'll either make your own FIFO design (the resource effcient solution) or use temporary storage registers for write words 1 to 4 and write the the complete data together with word 5 to the FIFO.
 
i mean that i want to read all the 5 data inputs at a time ,, "not writing one data and then reading it" as per how i programed in the above main program(#1).
 

In contrast to what I assumed in my previous post, I see that e.g. the Quartus FIFO IP does support different read and write word widths, if you have a write size of 32 bit as your code suggests, you should have 5*32 = 160 bit read size, as already suggested by sharath666.
 
You can use your modified state machine...to handle the writes...
The new FIFO you generated will have a read width of 32*5. Pass this data outside your top module danger1 through the port dataout as you have already done...
 
@sharath666: then at the u0: component instantiation , Expression dataout has 128 elements ; formal dout expects 32 elements only na ?? mismatched width?? how to deal it!!!
 

in wr_clk we write about write states and at rd_clk we write about read states ?? is that it? no its not happening.
 

no if we use independent clocks in xilinx coregen fifo generator , i thinking we need to create a state machines on all writes states at the process(wr_clk) , and reading all the states at the process(rd_clk) ,is that it?? i thought but its not happening.
 

You are supposed to write using wr_clk and read using the rd_clk. What do you mean by it's not happening? You still haven't made it clear what the problem is, or provided the code and testbench that you are running that has a problem that you can't figure out.
 

my code for writing 5 data serially and reading them at the time using independent clocks in xilinx corer fifogenrator., im not able to read 5 data at a same time .



Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_misc.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity fifo_5r is
	port(	reset: in std_logic;
			wr_clk: in std_logic;
			rd_clk: in std_logic;
			a: out std_logic;
			b: out std_logic;
			dataout: out std_logic_vector(31 downto 0);
			full: out std_logic;
			almost_full: out std_logic;
			empty: out std_logic;
			almost_empty: out std_logic;
			rd_data_count: out std_logic_vector(10 downto 0);
			wr_data_count: out std_logic_vector(10 downto 0);
			prog_full: out std_logic;
			prog_empty: out std_logic
			  );
end fifo_5r;

architecture Behavioral of fifo_5r is

signal count : std_logic_vector(31 downto 0 );
signal din : std_logic_vector(31 downto 0 );
signal wr_en : std_logic;
signal rd_en : std_logic;

type state_type is (rst1,write1,write2,write3,write4,write5,read1);
signal state,state2 : state_type;

component fifo_generator_v6_2
	port (
	rst: in std_logic;
	wr_clk: in std_logic;
	rd_clk: in std_logic;
	din: in std_logic_vector(31 downto 0);
	wr_en: in std_logic;
	rd_en: in std_logic;
	dout: out std_logic_vector(31 downto 0);
	full: out std_logic;
	almost_full: out std_logic;
	empty: out std_logic;
	almost_empty: out std_logic;
	rd_data_count: out std_logic_vector(10 downto 0);
	wr_data_count: out std_logic_vector(10 downto 0);
	prog_full: out std_logic;
	prog_empty: out std_logic);
end component;

begin
a<=wr_en;
b<=rd_en;

process(wr_clk,reset)
  begin
   if(wr_clk'event and wr_clk='1') then
      if(reset ='1') then
		count <= (others=>'0');
      elsif(wr_en= '1') then
		count<= count + 1;
		end if;
     end if;
	 end process;

process(wr_clk)
begin
if(wr_clk'event and wr_clk='1') then
   if (reset='1') then
	 wr_en<= '0';
	 rd_en<='0';
     state<= write1;
	  else
	     case (state) is 
    
   	                       when rst1=>
						  wr_en<= '0';
						 rd_en<='0';
					         state<=write1;
      				when write1=>
					              wr_en<='1';
                                                        rd_en<='0';                             
                                                   state<=write2;
				when write2=>
					              wr_en<='1';
                                                      rd_en<='0';                             
                                                 state<=write3;
				when write3=>
					              wr_en<='1';
                                                     rd_en<='0';                             
                                                state<=write4;
                               when write4=>
					              wr_en<='1';
                                                      rd_en<='0';                             
                                                  state<=write5;
                               when write5=>
					              wr_en<='1';
                                                  rd_en<='0';                             
                                               state<=rst1;
				when others=> 
					            state <= rst1;
									
	     end case;
	  end if;
end if;	
end process;

process(rd_clk)
begin
if(rd_clk'event and rd_clk='1') then
   if (reset='1') then
	 wr_en<= '0';
	 rd_en<='0';
     state2<= write1;
	  else
	     case (state2) is 
    
   	            when rst1=>
				   wr_en<= '0';
				 rd_en<='0';
				 state2<=read1;
          	when read1=>
				   wr_en<='1';
                                   rd_en<='0';                             
                                 state2<=rst1;
		 when others=> 
		                 state2 <= rst1;			 
         end case;
	end if;
end if;	
end process;
U0 : fifo_generator_v6_2
		port map (
			rst => reset,
			wr_clk => wr_clk,
			rd_clk => rd_clk,
			din => count,
			wr_en => wr_en,
			rd_en => rd_en,
			dout => dataout,
			full => full,
			almost_full => almost_full,
			empty => empty,
			almost_empty => almost_empty,
			rd_data_count => rd_data_count,
			wr_data_count => wr_data_count,
			prog_full => prog_full,
			prog_empty => prog_empty);
 end Behavioral;
 

In case the write and read clocks are different. you need to arrive at the correct sequence of events i.e. you need to exactly know when to assert wr_en and rd_en. In your case, rd_en has to be asserted everytime the count is a multiple of 4.
In your latest code, you are never asserting rd_en. Furthermore you are driving rd_en from 2 always blocks which is incorrect. Avoid driving rd_en from the always block triggered by wr_clk.
I would suggest you to draw a timing diagram for this code to understand things better or rather compulsorily draw one...
 

in my latest code i have asserted rd_en in the always block . i think my output is this is it!!!!**broken link removed**
 

The OP is also generating the wr_en in the rd_clk domain, which won't work.

I don't think the OP understands asynchronous/synchronous design, I also suspect they probably don't understand hardware design.

Without a clear specification of the requirements beyond "I have 5 input words written sequentially and 1 output word (equal to 5 of the input words) read". It's impossible to determine which solution you should use. As it is you are flailing around randomly trying things without thinking about what your requirements are. Things like write/read ratios, bursting, clock rates, latency, etc. have not been addresses or defined.
 

i hv done the simulation i think i did it , i need to approve frm my sir , if at all any problem ill ask your suggestions, thanku every one for all ur support .
 

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