fft processor in verilog coding with radix2 and radix 4

Similar threads

• C

  need help with verilog coding a morse code to ascii decoder

  • Started by combat5
  • May 28, 2024
  • Replies: 3

  PLD, SPLD, GAL, CPLD, FPGA Design
• R

  [Moved]Verilog issue with output even though condition is met(dice game)

  • Started by ralph_verilog
  • Oct 21, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  Which simulator should I use for verilog?

  • Started by electronicslab
  • Oct 26, 2024
  • Replies: 9

  PLD, SPLD, GAL, CPLD, FPGA Design
• I

  1st order sigma delta output is wrong verilog Cadence

  • Started by InvokeMeWell
  • Nov 10, 2024
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design
• J

  Connecting 7 in 1 Soil Sensor with GW1NSR-4C using UART

  • Started by Jainesh
  • Jul 20, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design