FFT Implementation on Spartan 3E xc3s100e-5vq100

allsey87 said:

If you are having mapping errors I would say you might want to look at rearranging stuff at the HDL level, as the autorouter for FPGAs is very good, and if it can't find a solution you may be out of luck for your current configuration.

Click to expand...

ads-ee said:

Not in my experience with dense designs. Which this one may be as the device the OP is using is rather small for the application. Also the indication from route implies the design is probably packing CLBs with unrelated logic, which map will do when the part is nearly full.

Click to expand...

FPGA SmartXplorer (tm) Version 13.2

----------------------------------------------------------------------
Strategy : MapTimingExtraEffort
----------------------------------------------------------------------
Run index : run1
Map options : -timing -ol high -xe n
Par options : -ol high
Total estimated power consumption : None (mW)
Status : Failed par
Current Best (Lowest) Timing Score : None
Current Best Strategy : None
----------------------------------------------------------------------
----------------------------------------------------------------------
Strategy : MapPhysSynthesis
----------------------------------------------------------------------
Run index : run2
Map options : -timing -ol high -xe n -register_duplication on -logic_opt on
Par options : -ol high
Total estimated power consumption : None (mW)
Status : Failed par
Current Best (Lowest) Timing Score : None
Current Best Strategy : None
----------------------------------------------------------------------
----------------------------------------------------------------------
Strategy : ParHighEffort2
----------------------------------------------------------------------
Run index : run4
Map options : -cm area -t 2
Par options : -ol high -t 2
Total estimated power consumption : None (mW)
Status : Failed par
Current Best (Lowest) Timing Score : None
Current Best Strategy : None
----------------------------------------------------------------------
----------------------------------------------------------------------
Strategy : ParHighEffort1
----------------------------------------------------------------------
Run index : run3
Map options : -cm area
Par options : -ol high
Total estimated power consumption : None (mW)
Status : Failed par
Current Best (Lowest) Timing Score : None
Current Best Strategy : None
----------------------------------------------------------------------
----------------------------------------------------------------------
Strategy : MapTiming1
----------------------------------------------------------------------
Run index : run5
Map options : -timing -ol high
Par options : -ol high
Total estimated power consumption : None (mW)
Status : Failed par
Current Best (Lowest) Timing Score : None
Current Best Strategy : None
----------------------------------------------------------------------
----------------------------------------------------------------------
Strategy : MapTiming2
----------------------------------------------------------------------
Run index : run6
Map options : -timing -ol high -t 9
Par options : -ol high -t 9
Total estimated power consumption : None (mW)
Status : Failed par
Current Best (Lowest) Timing Score : None
Current Best Strategy : None
----------------------------------------------------------------------
----------------------------------------------------------------------
Strategy : MapUseIOReg
----------------------------------------------------------------------
Run index : run7
Map options : -timing -ol high -pr b
Par options : -ol high
Total estimated power consumption : None (mW)
Status : Failed par
Current Best (Lowest) Timing Score : None
Current Best Strategy : None
----------------------------------------------------------------------

Click to expand...

ads-ee said:

You still need to post the resource utilization reports from map and you need to include the par report. You're probably running into a problem with LUT packing that is killing the router. You should also tell us what XST options are set, you may want to force area to be the primary goal of the synthesis and use the highest effort level.

Click to expand...

release 13.2 par o.61xd (nt)
copyright (c) 1995-2011 xilinx, inc. All rights reserved.

Abhi-pc:: Wed mar 12 19:48:18 2014

par -w -intstyle ise -ol std -t 1 ifft_map.ncd ifft.ncd ifft.pcf


constraints file: Ifft.pcf.
Loading device for application rf_device from file '3s500e.nph' in environment c:\xilinx\13.2\ise_ds\ise\.
"ifft" is an ncd, version 3.2, device xc3s500e, package fg320, speed -4
infoar:469 - although the overall effort level (-ol) for this implementation has been set to standard, placer will run
at effort level high. To override this, please set the placer effort level (-pl) to standard.
Vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
info:security:50 - the xilinxd_license_file environment variable is set to 'd:\new folder\xilinx ise design suite
13.2\spyral'.
Info:security:52 - the lm_license_file environment variable is set to 'd:\new folder\xilinx ise design suite
13.2\spyral'.
Info:security:54 - 'xc3s500e' is a webpack part.
Warning:security:43 - no license file was found in the standard xilinx license directory.
Warning:security:44 - no license file was found.
Please run the xilinx license configuration manager
(xlcm or "manage xilinx licenses")
to assist in obtaining a license.
Warning:security:42 - your software subscription period has lapsed. Your current version of xilinx tools will continue
to function, but you no longer qualify for xilinx software updates or new releases.

----------------------------------------------------------------------

initializing temperature to 85.000 celsius. (default - range: -40.000 to 100.000 celsius)
initializing voltage to 1.140 volts. (default - range: 1.140 to 1.320 volts)

infoar:282 - no user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and route will run in "performance evaluation mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the par report in this mode. The par timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".

Device speed data version: "production 1.27 2011-06-20".


Design summary report:

Number of external iobs 99 out of 232 42%

number of external input iobs 51

number of external input ibufs 51

number of external output iobs 48

number of external output iobs 48

number of external bidir iobs 0


number of bufgmuxs 1 out of 24 4%
number of mult18x18sios 16 out of 20 80%
number of ramb16s 2 out of 20 10%
number of slices 4386 out of 4656 94%
number of slicems 392 out of 2328 16%



overall effort level (-ol): Standard
placer effort level (-pl): High
placer cost table entry (-t): 1
router effort level (-rl): Standard

starting initial timing analysis. Real time: 6 secs
finished initial timing analysis. Real time: 6 secs


starting placer
total real time at the beginning of placer: 6 secs
total cpu time at the beginning of placer: 6 secs

phase 1.1 initial placement analysis
phase 1.1 initial placement analysis (checksum:9abc59) real time: 8 secs

phase 2.7 design feasibility check
phase 2.7 design feasibility check (checksum:9abc59) real time: 8 secs

phase 3.31 local placement optimization
phase 3.31 local placement optimization (checksum:9abc59) real time: 8 secs

phase 4.2 initial clock and io placement
....
Phase 4.2 initial clock and io placement (checksum:937c926f) real time: 9 secs

phase 5.30 global clock region assignment
phase 5.30 global clock region assignment (checksum:937c926f) real time: 9 secs

phase 6.36 local placement optimization
phase 6.36 local placement optimization (checksum:937c926f) real time: 9 secs

phase 7.3 local placement optimization
....
Phase 7.3 local placement optimization (checksum:5db1a340) real time: 9 secs

phase 8.5 local placement optimization
phase 8.5 local placement optimization (checksum:5db1a340) real time: 9 secs

phase 9.8 global placement
..........................
.......................................................................................................
.................................
.............................................................................................................
............................................................................................................
........................................................................................................................
Phase 9.8 global placement (checksum:6fc2b19) real time: 51 secs

phase 10.5 local placement optimization
phase 10.5 local placement optimization (checksum:6fc2b19) real time: 51 secs

phase 11.18 placement optimization
phase 11.18 placement optimization (checksum:509a4c66) real time: 59 secs

phase 12.5 local placement optimization
phase 12.5 local placement optimization (checksum:509a4c66) real time: 59 secs

total real time to placer completion: 1 mins
total cpu time to placer completion: 57 secs
writing design to file ifft.ncd



starting router


phase 1 : 24557 unrouted; real time: 1 mins 6 secs

phase 2 : 18210 unrouted; real time: 1 mins 7 secs

phase 3 : 4895 unrouted; real time: 1 mins 11 secs

phase 4 : 4906 unrouted; (par is working to improve performance) real time: 1 mins 12 secs
warning:route:438 - the router has detected an unroutable situation due to local congestion. The router will finish the
rest of the design and leave one or more connections as unrouted. The cause of this behavior might be putting too
much logic into a single clb. To allow you to use fpga editor to isolate the problems, the following is a list of (up
to 10) such congested connections:
Congestion on : Omux(49337,1840) signal : Fft/comp_mult1/mul2/mmult_mult_out_submult_01_p_to_adder_b_1
congestion on : Omux(49337,1840) signal : Fft/twdf1<15>
congestion on : Omux(-50096,-54291) signal : Fft/comp_mult2/mul2/mmult_mult_out_submult_01_p_to_adder_b_5
congestion on : Omux(-50096,-54291) signal : Fft/comp_mult2/mul2/mmult_mult_out_submult_01_p_to_adder_b_1
congestion on : Omux(-43275,-51520) signal : Fft/comp_mult2/mul2/mmult_mult_out_submult_01_p_to_adder_b_7
congestion on : Omux(-43275,-51520) signal : Fft/twdf2<39>
congestion on : Omux(40869,4496) signal : Fft/twdf1<37>
congestion on : Omux(40869,4496) signal : Fft/twdf1<36>


phase 5 : 2 unrouted; (par is working to improve performance) real time: 7 mins 1 secs

phase 6 : 2 unrouted; (par is working to improve performance) real time: 7 mins 4 secs

phase 7 : 2 unrouted; (par is working to improve performance) real time: 7 mins 7 secs

total real time to router completion: 7 mins 7 secs
total cpu time to router completion: 6 mins 28 secs

partition implementation status
-------------------------------

no partitions were found in this design.

-------------------------------

generating "par" statistics.

**************************
generating clock report
**************************

+---------------------+--------------+------+------+------------+-------------+
| clock net | resource |locked|fanout|net skew(ns)|max delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clock_bufgp | bufgmux_x2y10| no | 2909 | 0.089 | 0.206 |
+---------------------+--------------+------+------+------------+-------------+

* net skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from clock skew which
is reported in trce timing report. Clock skew is the difference between
the minimum and maximum path delays which includes logic delays.

* the fanout is the number of component pins not the individual bel loads,
for example slice loads not ff loads.

Timing score: 0 (setup: 0, hold: 0)

asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
constraint | check | worst case | best case | timing | timing
| | slack | achievable | errors | score
----------------------------------------------------------------------------------------------------------
autotimespec constraint for clock net clo | setup | n/a| 17.458ns| n/a| 0
ck_bufgp | hold | 0.674ns| | 0| 0
----------------------------------------------------------------------------------------------------------


all constraints were met.
Info:timing:2761 - n/a entries in the constraints list may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; other constraints intersect with this constraint; or this
constraint was disabled by a path tracing control. Please run the timespec
interaction report (tsi) via command line (trce tsi) or timing analyzer gui.


Generating pad report.

2 signals are not completely routed. See the ifft.unroutes file for a list of all unrouted signals.

Warningar:100 - design is not completely routed. There are 2 signals that are not
completely routed in this design. See the "ifft.unroutes" file for a list of
all unrouted signals. Check for other warnings in your par report that might
indicate why these nets are unroutable. These nets can also be evaluated
in fpga editor by selecting "unrouted nets" in the list window.

Total real time to par completion: 7 mins 11 secs
total cpu time to par completion: 6 mins 31 secs

peak memory usage: 277 mb

placement: Completed - no errors found.
Routing: Completed - errors found.

Number of error messages: 0
number of warning messages: 3
number of info messages: 2

writing design to file ifft.ncd



par done!

- - - updated - - -

par report
=================================================
release 13.2 par o.61xd (nt)
copyright (c) 1995-2011 xilinx, inc. All rights reserved.

Abhi-pc:: Wed mar 12 19:48:18 2014

par -w -intstyle ise -ol std -t 1 ifft_map.ncd ifft.ncd ifft.pcf


constraints file: Ifft.pcf.
Loading device for application rf_device from file '3s500e.nph' in environment c:\xilinx\13.2\ise_ds\ise\.
"ifft" is an ncd, version 3.2, device xc3s500e, package fg320, speed -4
infoar:469 - although the overall effort level (-ol) for this implementation has been set to standard, placer will run
at effort level high. To override this, please set the placer effort level (-pl) to standard.
Vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
info:security:50 - the xilinxd_license_file environment variable is set to 'd:\new folder\xilinx ise design suite
13.2\spyral'.
Info:security:52 - the lm_license_file environment variable is set to 'd:\new folder\xilinx ise design suite
13.2\spyral'.
Info:security:54 - 'xc3s500e' is a webpack part.
Warning:security:43 - no license file was found in the standard xilinx license directory.
Warning:security:44 - no license file was found.
Please run the xilinx license configuration manager
(xlcm or "manage xilinx licenses")
to assist in obtaining a license.
Warning:security:42 - your software subscription period has lapsed. Your current version of xilinx tools will continue
to function, but you no longer qualify for xilinx software updates or new releases.

----------------------------------------------------------------------

initializing temperature to 85.000 celsius. (default - range: -40.000 to 100.000 celsius)
initializing voltage to 1.140 volts. (default - range: 1.140 to 1.320 volts)

infoar:282 - no user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and route will run in "performance evaluation mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the par report in this mode. The par timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".

Device speed data version: "production 1.27 2011-06-20".


Design summary report:

Number of external iobs 99 out of 232 42%

number of external input iobs 51

number of external input ibufs 51

number of external output iobs 48

number of external output iobs 48

number of external bidir iobs 0


number of bufgmuxs 1 out of 24 4%
number of mult18x18sios 16 out of 20 80%
number of ramb16s 2 out of 20 10%
number of slices 4386 out of 4656 94%
number of slicems 392 out of 2328 16%



overall effort level (-ol): Standard
placer effort level (-pl): High
placer cost table entry (-t): 1
router effort level (-rl): Standard

starting initial timing analysis. Real time: 6 secs
finished initial timing analysis. Real time: 6 secs


starting placer
total real time at the beginning of placer: 6 secs
total cpu time at the beginning of placer: 6 secs

phase 1.1 initial placement analysis
phase 1.1 initial placement analysis (checksum:9abc59) real time: 8 secs

phase 2.7 design feasibility check
phase 2.7 design feasibility check (checksum:9abc59) real time: 8 secs

phase 3.31 local placement optimization
phase 3.31 local placement optimization (checksum:9abc59) real time: 8 secs

phase 4.2 initial clock and io placement
....
Phase 4.2 initial clock and io placement (checksum:937c926f) real time: 9 secs

phase 5.30 global clock region assignment
phase 5.30 global clock region assignment (checksum:937c926f) real time: 9 secs

phase 6.36 local placement optimization
phase 6.36 local placement optimization (checksum:937c926f) real time: 9 secs

phase 7.3 local placement optimization
....
Phase 7.3 local placement optimization (checksum:5db1a340) real time: 9 secs

phase 8.5 local placement optimization
phase 8.5 local placement optimization (checksum:5db1a340) real time: 9 secs

phase 9.8 global placement
..........................
.......................................................................................................
.................................
.............................................................................................................
............................................................................................................
........................................................................................................................
Phase 9.8 global placement (checksum:6fc2b19) real time: 51 secs

phase 10.5 local placement optimization
phase 10.5 local placement optimization (checksum:6fc2b19) real time: 51 secs

phase 11.18 placement optimization
phase 11.18 placement optimization (checksum:509a4c66) real time: 59 secs

phase 12.5 local placement optimization
phase 12.5 local placement optimization (checksum:509a4c66) real time: 59 secs

total real time to placer completion: 1 mins
total cpu time to placer completion: 57 secs
writing design to file ifft.ncd



starting router


phase 1 : 24557 unrouted; real time: 1 mins 6 secs

phase 2 : 18210 unrouted; real time: 1 mins 7 secs

phase 3 : 4895 unrouted; real time: 1 mins 11 secs

phase 4 : 4906 unrouted; (par is working to improve performance) real time: 1 mins 12 secs
warning:route:438 - the router has detected an unroutable situation due to local congestion. The router will finish the
rest of the design and leave one or more connections as unrouted. The cause of this behavior might be putting too
much logic into a single clb. To allow you to use fpga editor to isolate the problems, the following is a list of (up
to 10) such congested connections:
Congestion on : Omux(49337,1840) signal : Fft/comp_mult1/mul2/mmult_mult_out_submult_01_p_to_adder_b_1
congestion on : Omux(49337,1840) signal : Fft/twdf1<15>
congestion on : Omux(-50096,-54291) signal : Fft/comp_mult2/mul2/mmult_mult_out_submult_01_p_to_adder_b_5
congestion on : Omux(-50096,-54291) signal : Fft/comp_mult2/mul2/mmult_mult_out_submult_01_p_to_adder_b_1
congestion on : Omux(-43275,-51520) signal : Fft/comp_mult2/mul2/mmult_mult_out_submult_01_p_to_adder_b_7
congestion on : Omux(-43275,-51520) signal : Fft/twdf2<39>
congestion on : Omux(40869,4496) signal : Fft/twdf1<37>
congestion on : Omux(40869,4496) signal : Fft/twdf1<36>


phase 5 : 2 unrouted; (par is working to improve performance) real time: 7 mins 1 secs

phase 6 : 2 unrouted; (par is working to improve performance) real time: 7 mins 4 secs

phase 7 : 2 unrouted; (par is working to improve performance) real time: 7 mins 7 secs

total real time to router completion: 7 mins 7 secs
total cpu time to router completion: 6 mins 28 secs

partition implementation status
-------------------------------

no partitions were found in this design.

-------------------------------

generating "par" statistics.

**************************
generating clock report
**************************

+---------------------+--------------+------+------+------------+-------------+
| clock net | resource |locked|fanout|net skew(ns)|max delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clock_bufgp | bufgmux_x2y10| no | 2909 | 0.089 | 0.206 |
+---------------------+--------------+------+------+------------+-------------+

* net skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from clock skew which
is reported in trce timing report. Clock skew is the difference between
the minimum and maximum path delays which includes logic delays.

* the fanout is the number of component pins not the individual bel loads,
for example slice loads not ff loads.

Timing score: 0 (setup: 0, hold: 0)

asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
constraint | check | worst case | best case | timing | timing
| | slack | achievable | errors | score
----------------------------------------------------------------------------------------------------------
autotimespec constraint for clock net clo | setup | n/a| 17.458ns| n/a| 0
ck_bufgp | hold | 0.674ns| | 0| 0
----------------------------------------------------------------------------------------------------------


all constraints were met.
Info:timing:2761 - n/a entries in the constraints list may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; other constraints intersect with this constraint; or this
constraint was disabled by a path tracing control. Please run the timespec
interaction report (tsi) via command line (trce tsi) or timing analyzer gui.


Generating pad report.

2 signals are not completely routed. See the ifft.unroutes file for a list of all unrouted signals.

Warningar:100 - design is not completely routed. There are 2 signals that are not
completely routed in this design. See the "ifft.unroutes" file for a list of
all unrouted signals. Check for other warnings in your par report that might
indicate why these nets are unroutable. These nets can also be evaluated
in fpga editor by selecting "unrouted nets" in the list window.

Total real time to par completion: 7 mins 11 secs
total cpu time to par completion: 6 mins 31 secs

peak memory usage: 277 mb

placement: Completed - no errors found.
Routing: Completed - errors found.

Number of error messages: 0
number of warning messages: 3
number of info messages: 2

writing design to file ifft.ncd



par done!

Click to expand...

WARNING:Route:438 - The router has detected an unroutable situation due to local congestion. The router will finish the
rest of the design and leave one or more connections as unrouted. The cause of this behavior might be putting too
much logic into a single CLB. To allow you to use FPGA editor to isolate the problems, the following is a list of (up
to 10) such congested connections:

Click to expand...