FFT design choices - bitsize and implementation

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Hi all. I am rather new to the domain of digital signal processing so I would like to know how a seasoned veteran handles this design.

I have a 1-bit signal stream, and need to take a 1024-point fixed point FFT. Worst case the signal could be a constant 0 or 1.
* How do you select the number of bits required for the FFT?
* Can the bitsize at input or output be different.
* How do you scale the input signal, to prevent overflows?
* Are there any implementations that take advantage of the limited dynamic range at the input to minimize the FPGA footprint?

Thanks!
 

Hi,

Let's start with the input signal.
It's rather unusual to use just 1 or 0 as input signal.
Where does it come from? Maybe from a modulator...
Maybe it is coded somehow...so it can be transferred into more meaningful values.

An FFT output is in frequency domain.
Therefore it makes sense that you consider
* input data rate,
* output frequency resolution
...it could help if you tell us what's the purpose of the FFT, what informations are you after?

Klaus
 
Right on track!

The 1 bit input is indeed a bit strange. It comes from a 1-bit digitizer from a GPS front-end. The GPS signals are under the thermal noise and need to be demodulated with processing gain. Therefore the stream is in fact random noise.

The goal of the FFT is searching the satellite that are in view and with what SNR. This can be done by taking correlating in TD, or FFT, multiplying the signal with the gold code in the FD and iFFT. The second is what I would like to implement.

Output frequency resolution: sampling rate is 2.5MSamples, bin around 2.5kHz. I might need finer resolution but that's for later.
 

I'm no so familiar with GPS signal processing to decide if it's reasonable to perform a fft before decimation, but it's of course possible.

Just looking at the DC line, I guess up to 10 output bits can be significant, for a random signal probably less. Having different input and output width is generally possible with fft. Dynamic output scaling (common exponent for output data) is often performed by fft cores to keep the output below saturation.

Any fft implementation designed for a specific input word width takes advantage of reducing the dynamic range to the actual requirements.
 
Decimation is not possible because the chirp rate is 1mbps.

Do you mean that the dynamic scaling is done automatically by the FFT core? How does this work for a single-shot FFT? how is the dynamic scaling done if there's no dynamics involved?

Is it a correct working assumption that it is better to always use an FFT-core from the supplier in case you are working on an FPGA, because the IP is optimized for their specific architecture?
 

Dynamic scaling can be performed during the FFT calculation depending on the intermediate result.

I believe that it's generally preferred to use a vendor FFT core. But I'm not sure if it's prepared for 1 bit input.
 
For Decimation , I'm think the new chip in THz from Ti can cope with this problem . But depend on budget, it's worth upon !

And Implementation = Implant +/to Table .
 

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