[SOLVED] FFT 7.1 core outputs are the same

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity connect is 
port(Data : in std_logic_vector(3 downto 0);
			clock : in std_logic;
			Re_part : out std_logic_vector(7 downto 0);
			I_part :out std_logic_vector (7 downto 0);
			reset : in std_logic);
end connect;



architecture Behavioral of connect is
component fft is
port (
	clk: in std_logic;
	sclr: in std_logic;
	start: in std_logic;
	xn_re: in std_logic_vector(7 downto 0);
	xn_im: in std_logic_vector(7 downto 0);
	fwd_inv: in std_logic;
	fwd_inv_we: in std_logic;
	scale_sch: in std_logic_vector(7 downto 0);
	scale_sch_we: in std_logic;
	rfd: out std_logic;
	xn_index: out std_logic_vector(3 downto 0);
	busy: out std_logic;
	edone: out std_logic;
	done: out std_logic;
	dv: out std_logic;
	xk_index: out std_logic_vector(3 downto 0);
	xk_re: out std_logic_vector(7 downto 0);
	xk_im: out std_logic_vector(7 downto 0));
end component;

component QAM is
 
port ( data_in : in  STD_LOGIC_VECTOR (3 downto 0);
           im_part : out  STD_LOGIC_VECTOR (7 downto 0);
           real_part : out  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC;
			  start_out : out std_logic);
end component;

signal str :std_logic;
signal imag, re : std_logic_vector(7 downto 0);
signal const :std_logic;
signal clear :std_logic;

begin

stage1 : QAM
port map(Data, imag, re, clock, str);

stage2 : fft
port map( clk=> clock, sclr=> clear, start=>str, xn_re=>re ,xn_im=>imag,
 fwd_inv=>'1', fwd_inv_we=>'1' ,scale_sch=>"00000000",scale_sch_we=>'1',xk_re=>Re_part,xk_im=>I_part);


process(clock,clear,reset)
begin
	if(reset='1') then 

	clear<='1';	
	end if;
	
end process;
end Behavioral;