Feedback mux in clock gating

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booblik

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In a few papers I saw the usage of a feedback mux for clock-gating. How can it be used for clock-gating, if the original clock is still connected, and feeding, the DFF?



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When the CE input is 0, the output of the mux is Q, so that the FF will hold its present state on every clock, i.e., no change even though the clock is still running. When CE=1, the ouput of the mux is D, and the Q output will follow D on every clock edge.
 

Hi,

We normally use clock gating for reducing power. So even if input at D is the previous value and the original clock is still feeding the DFF. How does it reduce the power??

So how does Feedback muxes help save power?
 

When signals are toggling, there is a dynamic current. If the Q output is not toggling, you'll reduce the power. Physically, power is required because of the current required to charge capacitances.
 

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    booblik

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