[SOLVED] Feedback DAC linearity specs for a CTDSM ADC

[Ans5671]

Hello, I am designing a multi-bit feedback DAC for a CT-DSM ADC. I want to know what is the linearity specification requirement for SNDR ~ 90db of the CTDSM ADC. My understanding says that since the DAC errors fall in the STF path, its linearity should be ~ 90db. How can one obtain such high SNDR (= 14-bit ENOB) with a 4bit DAC?

 

[sutapanaki]

In this case you want the levels of the 4 bit dac to be 90dB linear, which means that the error between the output level of the dac and its ideal value should not be more than an LSB at the 15 bit level.

 

[Ans5671]

So, we check for the linearity of the DAC when it is in the feedback of the CTDSM or it could give 90dB linearity when tested as a standalone DAC?
I am confused as how can we get 90dB linearity from a 4bit DAC?

 

[sutapanaki]

How about you run DNL/INL for the DAC and see if it is at the -90dB level or 15 bit dac?

 

[Ans5671]

I have added a calibration circuit. With that, the INL has come close to 13 bits. I could put in the effort to reduce it further. Is that how we determine the linearity of the feedback DAC in CT-DSM and not the SFDR test with sinusoidal input?

 

[sutapanaki]

That is one possible way. In the CTSD you also have noise shaping which removes noise from the signal bandwith and can revеаl tones from nonlinearity. If you test the dac stand alone with a sine input and without shaping the noise, then the tones are just buried in the quantization noise. That's why I suggested doing INL/DNL.