fault model in vlsi testing

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vead

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I have little doubt
suppose
we have NAND gate = AND gate + not gate

suppose NAND gate have stuck at fault

to determine fault we will apply test vector to nand gate we don't have need to connect any extra fault model we consider that nand gate is faulty

I think I don't need to create fault model with nand gate on chip ?
 

Hello,
Can you please explain your doubt with more detail? I am confused becasue we dont connect any extra fault model. Stuck at is the fault model. So what do you mean by connect extra fault model?

By the way ATPG tool will understand the logic of NAND gate, so it will apply patterns accordingly.
 

thanks maulin for reply now I understood what is fault model

can you tell me how does we scan vlsi circuit I mean which tool we need to test vlsi circuit ,
 

Hello vead,
We usually do DFT to test the manufactured defects in the design,

DFT Implementation(scan-insertion)->DC compiler(synopsys),RC compiler(cadence),(inputs->Netlist,libraries, Output->scan netlist,STIL).



DFT ATPG(pattern generation)->Tetramax from synopsys and Encounter test from Cadence(Scan netlist,STIL are the inputs and patterns(SAF,TF) are the output)

As Maulin mentioned read some basic tutorial to understand the concepts.

Regards,
yuga
 

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