[SOLVED] FATAL: The following branches form a loop of rigid branches (shorts) when added to th

[georgemailo]

Hi. I want to design a verilog-a model of a two way switch. You can see the code below. When I run the simulation the "FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit..." error pops up. Searching on the internet I found something about switching branches in verilog-a which might cause this error but there wasn't any specific solution for it.
Do you have any solution to propose?

`include "constants.vams"
`include "disciplines.vams"

module TwoWaySwitch(p,n1,n2,cp,cn);
inout p,n1,n2;
input cp,cn;
electrical p,n1,n2,cp,cn;
parameter real vref=1.2;
parameter real vthreshold=vref/2;

analog
if (V(cp,cn)<vthreshold) begin
V(p,n1)<+0;
I(p,n2)<+0;
I(n1,n2)<+0; //maybe this is not necessary
end
else begin
V(p,n2)<+0;
I(p,n1)<+0;
I(n1,n2)<+0;
end

endmodule

 

[BradtheRad]

Try installing a low-ohm resistor in one or more wires.

It's a token resistance which is sometimes necessary so a simulator will permit such loops rather than call it an error.

 

[georgemailo]

Thanks. It worked!

 

[BradtheRad]

Great.

The same tactic might be necessary at other times too. Such as two capacitors in series, etc.