Hi everyone,
I'm using dc compiler to synthesize design. I can easily synthesize smaller designs but as designs grow in size dc_shell or design_vision close down with fatal error.
Is there a way to set up computer resources so that dc_shell won't fail but will take longer time? or anything along the lines
Then get it from Synopsys. Unless you are a designer of Design Compiler, you wouldn't know what caused fatal errors. Fatal errors happens mostly due to some issues in your design or Design Compiler and you can't go anywhere until you narrow down the issue.
Hi everyone,
I'm using dc compiler to synthesize design. I can easily synthesize smaller designs but as designs grow in size dc_shell or design_vision close down with fatal error.
Is there a way to set up computer resources so that dc_shell won't fail but will take longer time? or anything along the lines
Method you amy try:
1): Get more Physical memory for your server or PC.
2): Try to use dc_shell-t -64 mode if your CPU and OS support 64 bit mode.
3): Try to use down-top method to do synthesis. Synthesis small module first and stitch them up at top level. This will gain better timing and area.
Yes of cause if you're the designer of Design Compiler.
Bt the way; you may try "group" command. But it's better to create hierrchy by the RTL code designer.
Thanks.