fast verilog-A models

[eng_Semi]

Is there any hints that I should follow to fasten my verilog-A models ?

Thanks in advance

 

[freewing]

Can you make your question more specific? What kind of circuits and systems? Why do you need faster verilog-A models?

 

[eng_Semi]

I am building behavioral models for a PLL, but after connecting the loop and run simulation, it takes a lot of time.

I need fast behavioral models coz I think that one of the great advantages of behavioral models is low simulation time (compared with circuit level simulation).

I am using verilog-A with cadence tools.

Can any one help me ?

 

[freewing]

I did some pll simulation using verilog-A. I think the problem mostly comes from the transient analysis. Some points may help you.
1. In .tran analysis, if it's acceptable, try to use the analysis mode with least accuracy.
2. set time step to be larger in .tran analysis.