Fast settling time, low noise CMOS bandgap configuration

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tyanata

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Can any one propose fast setling time, low noise CMOS bandgap configuration.

Now we have such a problem, clock of the ADC couses glitches in the power supply.
And this disturbs behaviour of our bandgap. The bandgap is made with large area components in order to insure low noise. But these large components, increase setling time of the bandgap. And this is a problem for us because we need stable bandgap voltage when ADC starts Sampling.
 

bandgap problem

It seems difficult.
Perheps you need to consider tradeoff between noise and setting time.
 

Re: bandgap problem

Startup times less than 1us and good PSRR (<60dB) from DC to some 100MHz is difficult indeed and sorry your question is touching the critical IP domain. There are solution, sorry I could not offer more.
 

bandgap problem

Add a large cap in the reference output to form low pass filter.
 

Re: bandgap problem

Add capacitance to bias nodes to ensure bandgap is stable .Get more psrr for internal circuits than for the band gap to ensure switching do not effect the supplies.
 

Re: bandgap problem

1. use bypass capacitors
2. use the inner supply voltage that porvided by LDO
 

bandgap problem

I think the high frequency gliches caused by the ADC will have little influence on ADC
 

Re: bandgap problem

if power is not a main issue, maybe use chop modulation to achieve low noise bgp instead of large trans?
 

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