Fast EDA software for PLL full chip level simulation

[crazy_analog]

Any idea about PLL full chip level simulation?
It takes very long time to lock but i need to run simulation until PLL lock.
Do you know any fastest eda software?

 

[mpig09]

Re: PLL simulation

Dear crazy_analog :

You can use eldo to simulate.

mpig

 

[MSSN]

Re: PLL simulation

The solution is to write behavioral models for the non-critical blocks, to decrease the simulation time

 

[khouly]

Re: PLL simulation

yeah ,
u can use a beavioral models for the divider to speed up the simulation , i have seen the ADMS simulator of mentor , reduce the time of the PLL simulation very mch by using verilog model of the divider

khouly

 

[hung_wai_ming@hotmail.com]

PLL simulation

Yes, use RTL to replace divider in models then u can simulate much faster. Honestly, I would say 3 days is almost enough for a typical PLL to lock

 

[waxtomato]

PLL simulation

using ultrasim or nanosim, it much faster

 

[evence]

PLL simulation

If PFD and charge pump can opreate reliably at 100 times Fref. Change reference frequency to 100 times and scaling feedback divider ratio and filter capacitor to 1/100.

 

[jinnose]

PLL simulation

Use HSIM. Define all digital circuits as digital and define analog circuits such as loop filter as analog, then it will be at least 100 times faster than spice simulation.