yuvalkesi
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Hi,
1. I have a signal which is generated in fast clock domain. I need to pass this signal to a slow clock domain.
I have an idea, I wanted to be sure this is the correct way to do it.
I thought about making this signal longer (using a state machine with the fast clock) and then deriving it (with 2 FF's using the slow clock) making a synchronizer, and then pass along the derived signal to the slow clock domain.
something like that:
Is this the correct way doing it or is there anothe more 'code' friendly way?
2. I have an address bus generated in fast clock domain, and I need to pass it along to a slow clock domain.
In order to avoid using complicated methods to derive a bus (using hand shake mechanism, etc.) I thought about generating an 'enable' signal in the fast clock domain, and then, using the method described above (in Q'1), passing the fast domain address bus to the slow domain BUT and only but the slow signal (like d3_rd) is generated.
Is this the correct way doing it or is there another more 'code' friendly way?
Thanks!
1. I have a signal which is generated in fast clock domain. I need to pass this signal to a slow clock domain.
I have an idea, I wanted to be sure this is the correct way to do it.
I thought about making this signal longer (using a state machine with the fast clock) and then deriving it (with 2 FF's using the slow clock) making a synchronizer, and then pass along the derived signal to the slow clock domain.
something like that:
Code:
process (slow_clk, clr)
begin
if clr = '1' then
d1_rd <= '0';
d2_rd <= '0';
d3_rd <= '0';
elsif rising_edge(slow_clk) then
d1_rd <= long_rd; -- after SM to make it longer
d2_rd <= d1_rd;
d3_rd <= d2_rd; -- pass d3_rd to the slow clock domain
end if;
end process;2. I have an address bus generated in fast clock domain, and I need to pass it along to a slow clock domain.
In order to avoid using complicated methods to derive a bus (using hand shake mechanism, etc.) I thought about generating an 'enable' signal in the fast clock domain, and then, using the method described above (in Q'1), passing the fast domain address bus to the slow domain BUT and only but the slow signal (like d3_rd) is generated.
Is this the correct way doing it or is there another more 'code' friendly way?
Thanks!