During stuck-at testing, what will happen to false and multicycle paths from the functional logic. Will stuck-at testing take them as faults? How does ATPG tool handle false and multicycle paths?
Often, the false and multi-cycle paths from functional mode aren't relevant in scan mode, as scan will be run at a different (lower) frequency, without those constraints.
False paths are not covered in ATPG as those paths are not accesses.
Multi-cycle paths are covered by some ATPG techniques called sequential ATPG engine.
STA team also need to take care false path and multi-cycle path during testing timing closure.