start bit sampling data
Hi,
I'm sure you are aware of the conventional way of correctly receiving a byte packet with start and stop. Oversampling (8x or 16x) the datarate, and once the falling edge of the start bit is detected, the receiver waits 1/2 the bit-time (so, if you oversample by 16x, you wait 8 clocks). This way, you are looking in the middle of the start bit. You then simply delay the clock 16x, so you 'look' or 'sample' at the middle of the first bit.
I've done that method myself many times in logic, and its pretty damn reliable, so long as both clocks at the Tx and Rx are within 5% of each other.
Anyway, if you are planning on receiving packets at a
variable, or
unknown bitrate then maybe a PLL would be best. I personally tend to avoid them, because I don't have much experience with them, and I can generally do it all in pure logic (using counters, shift-registers etc..).
One thing though, looking at your diagram, I assume you are trying to 'syncronise' your clock with the incoming data instantly. By that, I mean without 'training' the PLL. In most cases, the first part of a packet you send, when using a PLL in the receiver, is a 'preamble'. Its usually for 'radio' links, but it also trains the PLL for the incoming datarate, allowing it to 'lock-on' before any real useful data arrives.
So, seeing as its christmas
I'll try and be of some use.
Q1. You can use a DPLL of course! But, it all depends on costs, the datarate of the system (variable, fixed, high, low etc...) and how complicatied you wish to make it. Using a PLL will require you to send a few 'dummy' packets as a training sequence, like 10101010.
A 'suitable' chip? As I said, I don't really know about PLL's, but I've used this once, with great success:
https://www.fairchildsemi.com/ds/74/74VHC4046.pdf
And its a 74 series logic chip, cheap and easy to get hold of. Also, theres plenty of reference designs for this IC on the web. It has a built-in VCO, that is tuned by external components up to 12Mhz.
Q2. The datasheet should get you started on a basic design. But read carefully about 'lock-times', that will tell you have many 'packets' you'll have to send, before you can start receiving data reliably (ie: not garbage).
There you go, I would strongly recomend the 'oversampling' idea, if its suitable. You'll 'lock-on' to the data instantly, at the start bit, and you can always use this setup to output a clock, just like in your diagram. A microcontroller, CPLD, FPGA, even a PAL could do it.
Hope this helps, good luck.
BuriedCode.