Failure of switched Mains product after isolation (hipot) testing

[cupoftea]

Hi Guys,
Its a pretty normal setup that our northern UK customer has.
Common as a Drapers Loaf, many would say.

But our Northern UK customer sees
failures of their main_PCB which seem to occur after the product has
been 4kV Flash tested on their production line. (They literally 4kV flash test every product on production.)

The product is basically 4 single phase mains trailing edge switches on a Main_PCB.
The switches are each cascaded TO247 FETs (source to source).
So single phase mains goes into the product, and gets put back out through these 4 channels...and so these switched
mains channels then go out of the product.. and to other things.

The gate drive for the 4 FET pair switches is via optocoupler. Each opto switches a 14v rail...onto the
gate to turn the FET switches ON.

The 14V rails (obviously four of them, one for each FET switch pair), come from a multi-output offline flyback
This flyback opto_regulates one of the 14v rails, and the others are supposed to just follow suit..
..because they are on the same transformer. This offline flyback is courtesy of an LNK3604.

The Main_PCB also has a zero crossing circuit, which reports zero crossings to the micro via opto. This multi output
flyback also gives isolated bias power to the mains zero cross cct. In fact...this is the only regulated rail of the multi output
flyback, and its opto regulated.

The micro drives the spoken_of opto's which phase switch the FET switchs.
(The micro is perched on a wee daughter board which is ribbon_cable_fed from the main_PCB.)

Bias power for the board comes from an offline 24V flyback secondary. This flyback
is on a different PCB. On the Main_PCB that we speak of, this 24v gets bucked down to give the 3v3
for the micro.

A CAN bus also comes to the PCB.

The Main_PCB sits in an earthed metal enclosure. The spoken of TO247 FETs are screwed to this earthed metal enclosure and
have insulation pads between them and this enclosure.

I am baffled at the isolation testing, because the product puts out raw mains (albeit phase switched).
So how can you make it safe by isolation hipot testing on production? It puts out raw mains(!)

We are going to visit their factory tomorrow in Northern UK, to see how they are (4kV) isolation testing the product.

Presumably they are testing for 4kV of isolation between the 24V rail and all the comms input lines etc
to the raw mains Line and neutral.

From speaking to them, I get the impression that they are also testing for 4kV of isolation between the earthed
enclosure and all the other nets on the PCB (line , neutral, +24v, GND_of_the_+24v, etc)

So have you any tips for us on this? And why are they 4kV isolation testing every product on production?

By the way, the FET switches don't have Zener protection of the (isolated) FET gates....

 

[cupoftea]

So basically, it doesnt make sense that one of the MOSFETs often fails after flash test, when the flash test doesnt put any voltage on any of the mosfet.
Also, it is unknown why every single production unit is getting the full 3.5kV flash test.
Surely a 500V isolation test is all thats needed?

 

[KlausST]

Hi,

ESD?
During storage, delivering, handling, assembling, testing ..

Klaus

 

[cupoftea]

ESD?

thanks ...that could indeed be it.
But they have said...if it was ESD then why did it work before being flash tested?

 

[KlausST]

Hi,

ESD may cause late / long term faliure.
It still could be ESD during or even after flash testing.

Klaus

 

[cupoftea]

Thanks, do you think a flash test could instigate an ESD failure of a fet? (even though it doesnt apply "obvious" voltages to the fet.
Maybe the sudden application of the flash test voltage gets through stray capacitances and ends up overvoltaging the Vgs of the FET?

 

[KlausST]

Hi,

for sure one has to expect the "hidden" paths, like capacitive coupling, inductive coupling, series inductance
In signal lines as well as in power supply (GND) lines.
Voltage in both directions, postive and negative.

You talk about Vgs ... but it also may be V_ds or similar.
Also to consider: is the FET fail really the primary fail? ... or is it maybe caused by the fail of the driver circuit / signals?

Klaus

 

[FvM]

I'm not aware of "flash testing" as commonly understood technical term. What kind of test according to safety standards is actually performed? AC or DC?

Surely a 500V isolation test is all thats needed?

I'd expect at least 1500 VAC/5 secs for 230/400 V CAT II mains input.

--- Updated Jul 18, 2024 ---

Might be that the test is inappropriate. You didn't yet explain what kind of isolation is implemented in the instrument, if parts of the the circuit are exposed (external LV interfaces or control elements).

 

[cupoftea]

What kind of test according to safety standards is actually performed? AC or DC?

Thanks, its a megger FT4 flash tester. Its AC. It can go up to 4kv.

Megger FT4 Flash Tester

national-instrument-hire.co.uk

They short Line_in,_neutral_LineOUTs...then do the flash test at 2kV between that and earthed enclosure (for 1 to 2 secs)...there must be "no arcing or flashover during the test".

They then short all the bias and control circuitry nets together, (at the connector) and then hipot test from that to the Line_Neutral_LineOUT....and do this at 4kv for 1 to 2 seconds...again,
"there must be no arcing or flashover during the test".

The thing is, the optos (PC357) are only rated to 3.75kv, and they are testing at 4kv.......so do you think they would see problems?
______________________________
Also, when the 2kV flash test is done between Line_Neutral_LineOUTs and the Earthed_Enclosure, then the
Isolated Control circuit nets are just "floating"...and as such, we suspect that maybe they are getting induced up to some ridiculously
high voltage during the flash test, and failures then possibly occur?....and this, we suspect, is causing the small number of control circuit failures that they have also seen post flash testing.
So do you think they would be better off bonding all the control circuit nets to neutral during the 2kV flash test (so that
the control circuit nets cant float up to dangerous levels) during the 2kV flash test?
_________________________

ESD may cause late / long term faliure.

...thanks, if i play the "ESD card" on them, their eyes will roll....because they handle FETs on other of their products and dont get failures. And in fact, they have a similar product to the one described, and it uses thyristors instead of FETs to do the switching, and they dont see failures on that one...and dont see the described control card failures.
___________________________
So the main failures they see are in the FETs...and they seem convinced that the failures happen after they have been flash tested.
But its doing my head in because i cant see how bad voltages can get to the fets from the flash test.
I mean, i dont hear of anyone selling flash testers which slowly raise the flash voltage up so that no dv/dt induced failures occur.
I dont hear of SMPS's that see FET failures post flash test.

 

[cupoftea]

Might be that the test is inappropriate. You didn't yet explain what kind of isolation is implemented in the instrument, if parts of the the circuit are exposed (external LV interfaces or control elements).

Thanks, but all the usual mains clearances and creepages have been adhered to. Nothing is "exposed" so to speak.

the FETs are all "high side" so to speak...they sit at the output of isolated flyback secondaries, and maybe somehow their gates (which arent zenered) are getting induced and a high vgs is killing them.....when the flash test is done?

 

[FvM]

Thanks for clarification. Preferably you would determine which components are damaged during test. I fear however that mains connected MOSFET can't resist surge tests without overvoltage protection, e.g. MOV or TVS diodes.

--- Updated Jul 18, 2024 ---

Other than bridge output transistors in mains connected inverters which are effectively protected by substrate diodes and DC link capacitors, your back-to-back series connected transistors have no built-in means to clamp transients

 

[cupoftea]

I fear however that mains connected MOSFET can't resist surge tests without overvoltage protection, e.g. MOV or TVS diodes.

Thanks, thats a great point, of course, in this case, we are just doing flash testing and not surge testing.

I guess the main question here is....Is it possible for an NFET in a normal offline SMPS to fail due to doing a flash (hipot) test?

 

[Easy peasy]

Sounds like they are zapping the P-N - impulse tests . . . but;

hi-pot tests are #1 P+N to output terminals ( ideally 3000 Vac 50Hz ), and #2 P+N to earth ( 2500Vac 50Hz ) - if #1 fails then the opto or the Tx or el-cheapo Y caps fail, either way should not affect the fet.

If there is a flash over from mosfet legs to earthed heatsink ( test #2 ) or something very similar - then yes you can kill the fet and possibly the gate drive too - or other things.

 

[FvM]

I guess the main question here is....Is it possible for an NFET in a normal offline SMPS to fail due to doing a flash (hipot) test?

Typically no because the voltage can't propagate to SMPS switches. But post #1 and post #2 don't talk about normal SMPS (e.g. flyback) switches but a kind of dimmer. Would need to see circuit and test procedure to be sure that a fraction of test voltage doesn't appear between drain and source.

 

[D.A.(Tony)Stewart]

Can you measure C @ 100 kHz before Hipot then dV/dt during with a probe shorted loop to measure dV/dt or measure peak current? PE ground often raises C coupling on isolated magnetics and Hipot stress on the smallest capacitance in the path.