spman
Advanced Member level 4
Hi friends,
What is problem in this design? The Clk net isn't detected in clock domains (constraint).
UCF :
I checked the design in FPGA Editor. The Clk isn't trimmed. It is routed to all CLBs. My FPGA is Spartan3.
What is problem in this design? The Clk net isn't detected in clock domains (constraint).
Code:
module top(InputClk, OutputClk, ...);
input InputClk;
output OutputClk;
wire ClkToDCM;
wire ClkToBUFG;
wire Clk;
IBUFG IBUFG_Ins(.I(InputClk), .O(ClkToDCM));
DCM DCM_Ins(.CLKIN(ClkToDCM), .CLKFX(ClkToBUFG));
BUFG BUFG_Ins(.I(ClkToBUFG), .O(Clk));
assign OutputClk = Clk;
always @(posedge Clk) begin
//state machine ...
end
Code:
INST DCM_Ins CLKFX_MULTIPLY = 3;
INST DCM_Ins CLKFX_DIVIDE = 1;
INST DCM_Ins CLK_FEEDBACK = NONE;