fail in post-layout simulation

[zgene]

no_notifier

HI,

I've finished APR using soc encounter, the timing analysis in setup time and
hold time are all ok for there is no negative slack.

And i use the extracted netlist and sdf for post-layout simulation. But there is one setup time violation,only one timing violation in one register, and cause the signal flow afterward fail.

how can i deal with that? re-synthesis and re-apr ?

thanks and regards!!

 

[nee_naresh04]

r u in online??

 

[xuanzhu]

Have you checked the timing by using the sign-off tool such as primetime or other vender tool. If you did it and you confirmed your timing check script is well, I suggest you check your simulation vectors, maybe they are too ideal. If you vectors are well, maybe you need modify your timing check script to increase the timing path coverage

 

[hgz]

use lower frequence simulation, if pass, may have setup time issue.

 

[aji_vlsi]

HI,

I've finished APR using soc encounter, the timing analysis in setup time and
hold time are all ok for there is no negative slack.

And i use the extracted netlist and sdf for post-layout simulation. But there is one setup time violation,only one timing violation in one register, and cause the signal flow afterward fail.

how can i deal with that? re-synthesis and re-apr ?

thanks and regards!!

This is often called "X-Poisoning" and one of the most time killers in Gate Level sims.

If you know why that Violation occurs and you are assured that it is a false alarm, then you have several choices such as:

+no_notifier - to turn OFF notifier so that No X gen

Selective turn off timing check

Simulators usually have commands to control timing checks - VCS and MTI for instance has tcheck TCL command

There are more ideas on the same topic, we cover that in our Comprehensive Functional Verification CFV class, see: www.noveldv.com for details. ALso we are planning for a 1/2 day focused session on "Gate Level Sim" in Bangalore, let me know if you are interested in attending it (ofcourse if you are in BLR) - entry *might* be free but limited number of attendees, write to me at cvc.training <> gmail.com if interested.

HTH
Ajeetha, CVC
www.noveldv.com

 

[Kulprashant]

Hi,
If u don't have any timing violation then for post layout simulation better dump the "SPEF" file and used for simulation and u will better results than SDF.

Regards,
Prashant

 

[rameshsuthapalli]

Hi All,

Please genrate the spef file in the encounter/some sign-off tool and genrate the sdf file in the primetime and do timing analysis with the primetime for setup with the max delay library using the spef.
if there is no violation that prime time is reporting still if the simulation is failing the mask the timing check in the simulation tool.

regards,
ramesh.s

 

[matthew_wang]

please use lower frenquency firstly, if works, then setup time violation, but I think you need to do some STA again.