Fading problem while displaying on VGA

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY VGA_SYNC IS
	PORT( clock_50Mhz: IN STD_LOGIC;
		horiz_sync_out, vert_sync_out, video_on : OUT STD_LOGIC;
		pixel_row, pixel_column : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 ));
END VGA_SYNC;
ARCHITECTURE rtl OF VGA_SYNC IS
SIGNAL horiz_sync, vert_sync, clock_25Mhz : STD_LOGIC;
SIGNAL video_on_v, video_on_h : STD_LOGIC;
SIGNAL h_count, v_count : STD_LOGIC_VECTOR( 9 DOWNTO 0 ); 
BEGIN
	-- Reloj de 25 MHz
	process (clock_50Mhz) is
	begin	
		if rising_edge(clock_50Mhz) then
			clock_25Mhz <= not clock_25Mhz;
		end if;
	end process;
-- video_on is High only when RGB data is displayed 
	
	PROCESS
	BEGIN
	WAIT UNTIL( clock_25Mhz'EVENT ) AND ( clock_25Mhz = '1' );
--Generate Horizontal and Vertical Timing Signals for Video Signal 
-- H_count counts pixels (640 + extra time for sync signals) 
-- Horiz_sync--------------------------------------------------- --------
-- H_count 0 640 659 755 799
--
--
	IF ( h_count = 799 ) THEN
		h_count <= "0000000000";
	ELSE
		h_count <= h_count + 1;
	END IF; 

 --Generate Horizontal Sync Signal using H_count 
	IF ( h_count <= 755 ) AND (h_count >= 659 ) THEN
		horiz_sync <= '0';
	ELSE
		horiz_sync <= '1'; 
	END IF; 
--V_count counts rows of pixels (480 + extra time for sync signals) 
--Vert_sync ------------------------------------------------ -------------- 
--V_count 0 480 493-494 524 
--
--
	IF ( v_count >= 524 ) AND ( h_count >= 699 ) THEN
		v_count <= "0000000000";
	ELSIF ( h_count = 699 ) THEN
		v_count <= v_count + 1 ; 
	END IF; 
	IF ( v_count <= 494 ) AND ( v_count >= 493 ) THEN
		vert_sync <= '0'; 
	ELSE
		vert_sync <= '1';
	END IF; 
	
	IF ( h_count <= 639 ) THEN
		video_on_h <= '1'; 
		pixel_column <= h_count; 
	  
	ELSE
		video_on_h <= '0';
	END IF; 
	IF ( v_count <= 479 ) THEN
		video_on_v <= '1'; 
		pixel_row <= v_count; 

	ELSE
		video_on_v <= '0'; 
END IF; 
video_on <= video_on_H AND video_on_V;

END PROCESS;
END rtl;

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pix_gen is
	port
	(
		clk50,video_on: in std_logic;
		pixel_x,pixel_y	: in std_logic_vector(9 downto 0) := (others =>'0');
		color: in std_logic_vector(2 downto 0);
		red_out, green_out, blue_out: out std_logic	
	);
end entity;

architecture rtl of pix_gen is
signal clk25: std_logic;
constant blue : std_logic_vector(2 downto 0) := "001";
constant red : std_logic_vector(2 downto 0) := "100";
constant yellow : std_logic_vector(2 downto 0) := "110";
constant green : std_logic_vector(2 downto 0) := "010";
constant black : std_logic_vector(2 downto 0) := "000";
constant white : std_logic_vector(2 downto 0) := "111";
begin
	process (clk50) is
	begin	
		if rising_edge(clk50) then
			clk25 <= not clk25;
		end if;
	end process;
	
	process (clk25, color, pixel_x, pixel_y, video_on)is
	begin
	if video_on = '1' then
		if rising_edge(clk25) then
			if color = red then
				if pixel_x < 640/2 and pixel_y < 480/2 then
					red_out <= color(2);
					green_out <= color(1);
					blue_out <= color(0);
				else
					red_out <= black(2);
					green_out <= black(1);
					blue_out <= black(0);
				end if;
			elsif color = green then
				if (pixel_x > 640/2 and pixel_x < 640) and pixel_y < 480/2 then
					red_out <= color(2);
					green_out <= color(1);
					blue_out <= color(0);
				else
					red_out <= black(2);
					green_out <= black(1);
					blue_out <= black(0);
				end if;
			elsif color = blue then
				if pixel_x < 640/2 and (pixel_y > 480/2 and pixel_y < 480 ) then
					red_out <= color(2);
					green_out <= color(1);
					blue_out <= color(0);
				else
					red_out <= black(2);
					green_out <= black(1);
					blue_out <= black(0);
				end if;
			elsif color = yellow then
				if (pixel_x > 640/2 and pixel_x < 640) and (pixel_y > 480/2 and pixel_y < 480) then
					red_out <= color(2);
					green_out <= color(1);
					blue_out <= color(0);
				else
					red_out <= black(2);
					green_out <= black(1);
					blue_out <= black(0);
				end if;
			elsif color = white then
					red_out <= color(2);
					green_out <= color(1);
					blue_out <= color(0);
				
			else 
					red_out <= black(2);
					green_out <= black(1);
					blue_out <= black(0);
			end if;
		end if;
	end if;
	end process;
end rtl;