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Extremely Low Power Datalogger

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burningmosfet

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Hello everybody i'm an electronic engineer with 3 years of experience in hw and fw design.
I'm going to design a low power data logger equipped with SD-card (SPI protocol), external RAM and small electronic for analog signal conditioning.

The key point of the design is that the DL has to be supplied with a small 3V battery so that its AVERAGE power requirement is about 1mA at 3V = 3mW (i know it's a suicide).

I'm aware that some peripherals could be current-greedy (for example the sd-card) but I think that powering the circuit only when you need it (for example for 100mS every 10 minutes) i could reach the goal (or approach it).

I'm going to choose the right MPU but i would like to receive some advice by expert designers for this essential step.

The main features of the MPU should be:

1) internal high precision RTC
2) ADC with >=12bit
3) ISR management in stand by mode (to keep low current consumption from MPU)
4) >=64K Flash
5) >=5K RAM
6) Low supply voltage range (from 1.8V to 3.6V)
7) >= 2 Standby mode (worthwhile if the internal peripherals can be individually switched off)
8) Fast wake up from standby
9) UARTS, SPI

I would be glad to receive advice, links or suggestions in this post, not only for what concerns the CPU, but also design criteria (for example the use of PLL as frequency multiplier to reduce the uA/Mhz etc ...).

Thank you very much !
 

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