extraction of synthesizable code from given code

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snehalkate

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Is there any software or tool with which i can separate out synthesizable and non sythesizable code from a given verilog code?
 

Is there any software or tool with which i can separate out synthesizable and non sythesizable code from a given verilog code?
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I'm pretty sure that there's no such thing.
The ability to tell which code can or cannot be synthesized to real logic is an integral ability of any synthesis tool - once the tool sees something "illegal" the implementation process stops with an error.
It certainly doesn't separate synthesizable and non synthesizable logic apart - this is your job.
 
Go through the warnings in the synthesis log to find out issues if any..That should be a good way to find out what is happening to your design..
 
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