Extraction of NMOS and PMOS parasitic capacitances

Hi guys,

There is anyone who can tell me how to extract the capacitances from the MOSFET?

I know that one can get the capacitances from the DCop Point but I think that those are not reliable and accurate. I'd like to measure it using another technique. I'd like to plot at the same time how the capacitances cgs, cgd, cds, cdb, csb, etc varies with respect to L, W, Vgs and Vds.

I am using cadence 6.

Kind regards.

Hi

just make layout and perform extraction operations with assura or calibre
Or, perhaps you have RFmos in your technology library and, in that case all parasitic capacitances of mos already included in model.

How can I do this? How can I extract those values? I need some of the parameters state in the previous post in order to do some estimations.

1. Layout
2. Extraction
3. Create tb for extraction view and measure searched capacitances (i usually do it in ac analysis)
4. Need sweep W,L? Repeat all operations.

It is just way, how i would do it (if rf models not available)

Hi sarge,

There is a missunderstanding.

When I say extract those values I mean to extract the values from the model. For example I need the value of the total gate capacitance to design a mosfet gate driver. I read that one could use the print op and select the capacitance that we want. However those values are being presented as a negative number. There is no negative capacitances so I don't know what is happening.

Sir, you are in a little trouble, if you find a systematic way to solve it tell me too.

First thing: because of the modelling technique used, don't be suprised when you see negative capacitances. Those are related to the charge conservation oriented modelling which is used in most models. Anyway, extracting cgb cgd or cgs might not give you what you're looking for. But there are exceptions, for example in saturation cgs is usually the real cgs.

My workaround to this problem is really measuring the capacitances with tran or ac sim. However, this is tricky, time consuming and bias dependent. And also if you use tran to do this, the longer the simulation more inaccurate it will get since the bias is changing. If you can find a better way to do this, share with me please.

Kemiyun, thanks for the tip. Regarding the negative capacitance one can ignore the "Minus" signal?

Now with respect to the capacitance extraction, I have searched through forums, google, papers, etc etc etc and the conclusion that I don't know if it is right was this one:

We can do I simple dc analysis and print the values using the calculator through the OP option. After that select the componnet and then choose the parameter that we want (in this case the capacitances).

This is the only conclusion that I could get. However I don't know, as I said, if it is accurated. I don't know if it is possible to get the capacitances values in another way.

I read that there are guys using the cgg (for example) to get the total capacitance at the gate.

For example, I have seen one guy getting the real capacitance from the model (RF transistors) through an S parameter simulation and then manipulating the results with Y matrix, etc. Then he ploted the CGS vs Freq. and one could see the effect of the frequency on the mosfet capacitances.

I saw in a tutorial (from a recgnized university from USA) where they have used the saved OP point (into a SCS file) to plot the capacitances as a function of the swept variaable (for example VGS).

Those capacitances are the intrinsic ones.

Well, taking into account this, I need to get an idea of the total input capacitance from my power stage (each transistor) in order to design the drivers.

From the tecnology manuals that I have for 130nm the manufacturer specifies there which TOX was extracted. I was wondering if I can compute the COX through the TOX and epsilon and with that get the CGS, CGD, CGB using the available expressions on the book for each operating point (triode or cut-off).

Do you have any suggestion on how to design the driver circuits? I'd like to have a starting point.

Regards.

Well you can't ignore the minus signs they are there for a reason. I'm just saying that under certain circumstances they really reflect the real values.

Why don't you both measure the cap in simulation and take the output of the OP analysis and compare them? That would clear things up. Just make sure that you have the bias you wanted before you do so.

When you start talking about total or effective capacitance at one node, you have to make measurements yourself. Because those are the terms you defined, simulator doesn't care about the total capacitance at a node at all.

Calculation is a good idea and it will give you insight about the problem but the problem is your results will always have an error. Simply because simulator uses much advanced models. If you are going to use the same models, why not just use the simulator itself?

I have a suggestion, read and lurk in ieeexplore library. There are extreme amounts of papers dedicated to optimization of different types of DC-DC converters. One good example is Analysis and Optimization of SC DC-DC converters written by Seeman, M. . However optimizing it doesn't imply that you have to calculate it and put 12.31213 um / 120nm nfet over there. It's more like finding a good enough solution, so in short, know what you want to have and tweak your circuit to achieve that, otherwise it gets too complicated too quickly.

Hi kemi. Thanks for the reply.

Grabbing your expression: "Calculation is a good idea and it will give you insight about the problem but the problem is your results will always have an error. Simply because simulator uses much advanced models. If you are going to use the same models, why not just use the simulator itself? "

and

"Why don't you both measure the cap in simulation and take the output of the OP analysis and compare them? That would clear things up. Just make sure that you have the bias you wanted before you do so."

This is precisely what I want to do. Simulate and get the capacitance at the GATE of the MOSFET. But HOW this is done? From what I read in several forums the methods that I encountered (that were not to much) are described in my previous post! Although I don't know if they are reliable.

Oh, I'm sorry I must've misunderstood the question then. You can connect an ac source to a node and use ac analysis to get the impedance then move to get capacitance part. However this gets complicated when there are more resistances and capacitances than you first assumed.

Another method is using a dc source and transient analysis. Voltage at the node should increase and the slope of it will give you the capacitance. People might disagree with me but resistor increases the offset but it doesn't do anything to the slope of increase or decrease. It's more straightforward to do it this way but you should be careful with the biasing points because caps are dependent on bias when a high level model is considered.

Using the print OP isn't enough then?

By the way, I got curious when I did a print op to a capacitance on a nmos transistor.

When I selected the Cgs and did the plot (who says Cgs, says the same for Cgg, Cb, etc) in the x-axis was the Width of the MOSFET. The capacitance was right in the point of the width of my transistor that is 1000um. However, I use the multiplier option in the properties of the transistor. This means that I must multiply the capacitance by 2?

Using the print op should be enough but it depends, if there are other things that are connected to the node, it's not going to give you a total effective capacitance. I thought you were asking about how to measure it.

I have no idea but I don't think you should multiply it by 2 if you are using m factor. But if you are using another multiplication tool provided by fab that depends on how that PDK is programmed.

Hi kemi,

Well, I don't know if you have ever used the m factor in candence. When you need larger transistors normally we use the m factor so that we can replicate the same transistor several times.

That said, since my transistor has a width of 2000u, I used a transistor with W=1000u and then m=2.

Now, the question is: the value of the capacitance that appears in the OP point should be multiplied by 2 (because I am using two transistor with a width of 2 - m=2) or not?

I thought you were asking about how to measure it.

Click to expand...

That's what I want to do. Besides the OP point there is another way?

Believe me I've used m factor . The thing I'm not sure about is that how it manipulates the dc op point (whether you need to multiply by 2 or not). I'm sure that the dc op point of a real transistor with width of 10u will not be equal to the transistor with 1u multiplied by 10. So I haven't done this part myself, put 2000u and 1000u*2 and compare, this is what I wanted to point out. They should be at least close to each other, but it will give you an idea if you need to multiply it.

I've explained how you can measure it with analogLib elements in one of the previous posts. Just for the reference measuring and OP point are not the same thing. Op point is calculated and it's the value used by the simulator. Measuring is putting necessary ideal elements to actually measure the capacitance or whatever you want just like real life, but simpler and faster .

Edit: By the way I forgot to say that, m factor does not multiply the transistors by putting many of them in parallel, if you are using the CDF parameter m. So you are not going to end up with two instances of the transistor if you use m factor. But if you use multiplication provided by PDK then it depends on PDK.