External Pull up on xilinx 9500xl?????

[Zerox100]

I am using an xc9500xl CPLD. It has a VCC equal to 3.3v maximum. I need a 5v TTL leve in some IOes. Is it possible to add external pullup to reach +5v standarda TTL level?

 

[alexan_e]

The XL series have 5v tolerant pins so you can use the 5v pullup without a problem but I don't think you will be able to get the 5v that you want.
I don't think thee is an open drain mode and that is what you need in this case.
When you drive the output with 3v then the 5v pullup will not help.
The only way I can think of is to use the pin as input when you want 5v so that the pullup wan force 5v and as an output when you want to ground the output.

Alex

 

[Zerox100]

What do you think about using in tri-state mode instead of '1' logic? I know it is possible!!! But i am not sure about maximum frequency you can use in this mode?

 

[alexan_e]

I have only made some simple projects and I haven't used anything similar so I don't know.

If you can set the output to high Z then the pulup will be able to set the output to 5v but I have no idea about the frequency.

 

[bking]

**broken link removed**

 

[RetroTechie]

I used Figure 1 construct in above link, with a Xilinx XC9572 (without -XL) successfully. Small Z80-based system, 10K pull-ups, 3.25 MHz clock.

See no reason why it wouldn't work with 9500XL family, since they have 5V tolerant I/O's. You could take an estimate of trace+total input capacitance, multiply with value of pull-up resistor to estimate low->high transition delay. Lower pull-up value if needed (up to a point, of course).