Apr 25, 2011 #1 D deepthi.reddy.912 Newbie level 5 Joined Apr 19, 2011 Messages 10 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,447 Is there any external clock generation scheme available in Xilinx ISE or in ModelSim or any sample vhdl code for providing synchronous clock for all pipelined stages in a combinational circuit? If so please help me.
Is there any external clock generation scheme available in Xilinx ISE or in ModelSim or any sample vhdl code for providing synchronous clock for all pipelined stages in a combinational circuit? If so please help me.
Apr 28, 2011 #2 R rhaynes Member level 5 Joined Feb 8, 2011 Messages 84 Helped 37 Reputation 74 Reaction score 37 Trophy points 1,298 Location Oceanside, CA, USA Activity points 1,996 Something like this??? signal i_clk : std_logic := '0'; process(i_clk) begin i_clk<= not i_clk after 10 ns; end process;
Something like this??? signal i_clk : std_logic := '0'; process(i_clk) begin i_clk<= not i_clk after 10 ns; end process;