Extending pulse width

[pashkatarakashka]

I have DMM which is producing pulse with duration of around few microseconds.
The pulse need to be sampled in PLC, which has sampling rate of 1ms.
In other words the cycle loop can't be reduced to microsecond resolution.
So it's impossible to reliably detect the pulse from DMM.

Could somebody recommend a simple TTL based circuit solution, which will be able to capture that microsecond resolution pulse and convert it into millisecond resolution pulse?

 

[barry]

You could use a 555 timer to generate a long pulse.

 

[KlausST]

Hi,

look for "monoflop" or "monostable multivibrator"

Klaus

btw: an internet search for "pulse extender circuit" gives more than 1 million hits with schematics and descriptions.

 

[crutschow]

A simple diode RC pulse stretcher may do what you want (LTspice simulation below):
What's the pulse rep rate?

 

[d123]

Hi,

Might not work as hoped as I haven't checked myself, that's why the upper NOT gate is dashed, to be added to source and sink faster. If it can, if low input needed for PLC, hex inverter would still have two unused gates to make use of one of them. The 555 suggestion would work as it seems only requirement is >1ms.

Apologies for 2.8 MB photo, 'phone doesn't seem to have option for reducing MB to kB.

 

[dick_freebird]

There are parts in the 74HC series that would be happy
to stretch a 5V pulse. Look at 74HC122 (single) or '123
(dual). Add a 5V "wall wart" and a couple of BNC connectors
and you're there (although I'd keep the output stub pretty
short as the HC series isn't going to drive 50 ohms to the
rail; a "TTL" input however may be forgiving of this, and
maybe OK thermally if you keep the rep rate down).

 

[pashkatarakashka]

What's the pulse rep rate?

300-400ms

 

[danadakk]

A solution, one chip, timing accuracy +/- 2% over T & V.

to
An alternative, advantage pulse in leading edge synch to output stretched edge.
Needs one instruction typed into C file, a start instruction. Otherwise code-less.
If pulse in rep rate > period out, each pulse in will truncate pulse out and restart it.

Other resources available onchip -

Note designs above can manage Pulse in << 1 uS easily.


Regards, Dana.

 

[crutschow]

Here's the circuit simulation with a 300ms pulse period:
Unless the PLC is sensitive to the pulse rise-time, it should work.

 

[danadakk]

Generally speaking slow risetime is a problem. Also terminating an input with large C
and possible damage to PLC input chip on power down. Adding a R between input
and C to limit peak discharge current prudent.

Schmidt trigger handles slow risetime. Unless PLC has that on its inputs.

https://www.ti.com/lit/wp/slla364a/slla364a.pdf?ts=1655941832120&ref_url=https%253A%252F%252Fduckduckgo.com%252F

Regards, Dana.

 

[crutschow]

Generally speaking slow risetime is a problem.

I know "generally speaking" it is, but it may not be for the PLC which is apparently just sampling the input.

Also terminating an input with large C
and possible damage to PLC input chip on power down.

That's simply solved by putting a small resistor (e.g. 1kΩ) in series with the PLC input.

 

[dick_freebird]

A question occurs to me, which is

"Can the PLC be set to "edge trigger" rather than "level
trigger, with slow response"?

I'm no PLC expert but seems like maybe there's a
"feature" like trigger noise rejection / debounce, for
the specific make/model, that might have options if
you peeled back the lid?