Expression evaluation in vhdl and verilog

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kommu4946

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hi ,
How verilog and vhdl expressions are evaluated.i am getting different results when the same code is written in verilog and vhdl.
the expression is:
d=(a+b)*p;
a,b,p are signed numbers of size 16 bits and d is the signed number with 32 bits.when a, b are 16384(decimal numbers) and p is 1229 .The vhdl simulator is giving output as -40271872 but verilog output is 40271872.I know that sum becomes 32768 which is out of range of -32768 to 32767 so that it is -32768*1229=-40271872 but why verilog is giving 40271872...
 

Code VHDL - [expand]
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[code]
signal d : signed( 31  downto 0  );
signal a:signed (15 downto 0);
signal b :signed (15 downto 0);
signal p:signed (15 downto 0);
...........
d<=(a+b)*p;
[/code]


the verilog code is
Code Verilog - [expand]
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[code]
wire signed[15:0]a,b,p;
wire signed[31:0]d;
........
assign d=(a+b)*p;
[/code]
 

IIRC, Verilog does length extension automatically when you do addition or subtraction. VHDL does not. You need to extend a and b before you add them.:

Code: 
signal d : signed(32 downto 0);

d <= ( resize(a, 17)  + resize(b, 17) ) * p;

You need a larger D signal to cope with the extra bit output from the addition.

Without the resize, you are getting rollover on the addition.
 
IIRC, Verilog does length extension automatically when you do addition or subtraction.
Click to expand...
The difference between VHDL and Verilog is that Verilog uses context-determined expression bit length in some cases. I'm not quite sure how it works in a composite expression like the present, apparently the left-hand side bit length is affecting the evaluation of the inner term. See Std 1800, Paragraph 11.6 Expression bit lengths
 

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Hey Thanks for your help.I have gone through context determined operators and self determined operators in verilog.Here i have simple question how the same code is synthesized in verilog and vhdl.
vhdl code
Code VHDL - [expand]
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entity sim_vhd is
    Port ( a : in  signed (15 downto 0);
           b : in  signed (31 downto 0);
           c : out signed (15 downto 0));
end sim_vhd;
 
architecture Behavioral of sim_vhd is
 
begin
c<= resize ((a+b/2**5),16);
 
end Behavioral;

verilog code is
Code Verilog - [expand]
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module sim_ver(
    input signed[15:0] a,
    input signed[31:0] b,
    output signed[15:0] c
    );
assign c=(a+b/2**5);
 
endmodule


when i synthsized above two codes ..i am getting macro statistics for vhdl
Macro Statistics
# Adders/Subtractors : 2
27-bit adder : 1
32-bit adder : 1

for verilog
Macro Statistics
# Adders/Subtractors : 2
28-bit adder : 2
My question is why in verilog 28 bit adder,why not 32 bit adder (because + is contex based operator,which has 32 bit operand in the expression) and why extra 27 bit adder (that may be for division) how division is synthesized..i am using xilinx 14.4
 

I don't know how /2**5 is done in Verilog. VHDL is consistent with algebra -- -(a/b) = (-a)/b = a/(-b), which implies some form of symmetric rounding. C does truncation (round to -inf). IIRC, verilog does the same.
 

The codes are different. If you discard the upper 16 bits in the VHDL code instead of using a resize operation, you get the same logic utilization as Verilog.
 

Code: 
architecture Behavioral of sim_vhd is
signal t:signed (31 downto 0);
begin
t<= (a+b/2**5);
c<=t(15 downto 0);


end Behavioral;
but still i am getting same as mentioned above...
why 28 bit adder in verilog and 27 bit adder in vhdl...can you please explain...
if the code is
Code: 
c<= (a+b(15 downto 0)/2**5);

the synthesis report becomes
Macro Statistics
# Adders/Subtractors : 2
11-bit adder : 1
16-bit adder : 1
 
Last edited:

The second code is of course completely different, cutting higher bits from input b.

I see same number of logic elements in synthesized logic for Verilog and VHDL with result truncation, in so far I assume, the 27 versus 28 bits point is just a matter of RTL representation.

As preliminary conclusion, we see that different rules for expression bit length may result in different implemented logic when translating arithmetic between both languages, particularly with obscure expressions.

By the way, what's your exact intention with b/2**5, can't you use SHIFT_RIGHT(b,5)?
 

Thanks for your interest.....when i used shift_right function in vhdl code is synthesized to 32 bit adder only (i got rid off 27 bit adder).Similarly when i used arithmetic shift operator in verilog code is synthesized to 32 bit adder only.I came to know that /(division operator) is expensive in resource utilization than shifting operator..but still i have a doubt in verilog code
Code: 
assign c=a + (b>>>5)
//when i used above expression the fallowing warning comes
//Result of 28-bit expression is truncated to fit in 16-bit target
why not expression length 32 bits according to context determined expression rules...
 
Last edited:


(b>>>5) results in a 32-bit being reduced to 27-bit then the + results in a 28-bit result. Nothing odd about the way Verilog handles this.
 
ads-ee said:
(b>>>5) results in a 32-bit being reduced to 27-bit then the + results in a 28-bit result. Nothing odd about the way Verilog handles this.
Click to expand...
I got your point.Initially i thought that according this statement in ieee reference manual The arithmetic right shift shall fill the vacated bit positions with zeroes if the result type is unsigned.It shall fill the vacated bit positions with the value of the most-significant (i.e., sign) bit of the left operand if the result type is signed. I think After filling with sign bit,it is discarding that many number of bits.For a signed number it would give the same meaning(like if -2 can be 1110 for 4 bit,111110 for 6bit are same..etc).For a curiosity i just changed arithmetic shift to logical shift then bit expression length become 29 bits.logical shift fills with 0 which make the number unsigned ,32 bit being reduced to 28 bits(it is preserving only one extra 0 to indicate it is a unsigned number) then + results in 29 bit result.Am i thinking in the right direction?

Thanks every one...
 

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