Re: contamination delay
Hi,
You need to understand that VALID inputs take time to appear as VALID outputs. This delay (or time) is nothing but the propagation delay.
But INVALID inputs take a finite time (or delay) too to appear as INVALID outputs. This is known as Contamination delay.
If you think it from transistor level point of view, think of the threshold voltage of the transistor. But if you are thinking from Digital point of view, think of the Noise Margin analysis.
Actually speaking you need the contamination delay only while designing circuits, else you can assume it zero in your timing analysis.
Cheers!!!