Explanation of set_multicycle_path in Verilog code

[openwindows]

i am a little confusion of set_multicycle_path when i synthesis my design by dc,who can help me explain it by verilog code?


very thanks!

 

[roli]

set_multicycle_path -hold

Sure - :

=====================
always @(posedge clock or negedge Reset_n)
if !(Reset_n)
Enable <= 1'b0;
else
Enable <= !Enable;


always @(posedge clock or negedge Reset_n)
if !(Reset_n)
flop <= 1'b0;
else if (Enable)
flop <= !Flop;

====================
In the above, flop changes state every OTHER clock cycle.
So you could theorithically set for that 'flop' a multicycle path of 2 clocks (relaxed...)