explanation of how to translate C code into verilog

[keikaku]

I am brand new to Verilog. I am taking a course. If I am in the wrong place, please let me know.

I am trying to understand how to translate the following C code into Verilog. I just do not get how. Any help is appreciated.

x = 0;
for (i=0; i < 3; i++ ){
x = 2x + 1;
}

Any explanation of how to this can be done ? I suppose this is simple code, but Verilog seems difficult.

 

[dpaul]

That should be trivial, a simple internet search will give you the results, you can do that on your own!

The bigger question, do you want to compute the value of x (which I am assuming would be of type reg), on every rising edge of the clock or you want to have the computation under 1 clock cycle?

 

[FvM]

Formally, the code can be converted to verilog by replacing { } with begin end.
An iteration loop in Verilog describes however parallel logic, respectively it will be calculated at once. Otherwise you have to design a clocked sequence (finite state machine).
As the given code has constant parameters, it will be reduced by Verilog synthesis tool to a constant assignment x = 7.

 

[KlausST]

Hi,

while it is possible to translate C into verilog ... I still recommend to remind that
* C is a software language, where line after line is processed
* Verilog is a hardware description language, where all lines are processed in parallel

Thus C and Verilog have rather different timing output.
In C variables are updated line after line. The variable values are valid (at least for a short amount of time) until they become overwritten by another line .. some time later.
In Verilog this is different, because a variable value (result of a code line) may not be valid (not for a tiny moment), because it may be over ruled by a different line of code.

Verilog: Think as hardware. Don´t think as software at all.

Klaus

 

[danadakk]

Google "c code to verilog converter"....

But keep in mind tools not total solutions....


Regards, Dana.

 

[keikaku]

you are right, it should be "trivial." but if i knew how to do it i would not be asking this question here. while i do see there are conversion sites, they do not explain the process.

 

[keikaku]

Formally, the code can be converted to verilog by replacing { } with begin end.
An iteration loop in Verilog describes however parallel logic, respectively it will be calculated at once. Otherwise you have to design a clocked sequence (finite state machine).
As the given code has constant parameters, it will be reduced by Verilog synthesis tool to a constant assignment x = 7.

thanks for the response. i have been attempting to use the EDA Playground site to run the code using the "begin" and "end". i am not understanding what could be the issue. i attached a screenshot.

 

[FvM]

I'm not familiar with Eda playground, but your code is incomplete, it misses module header and end, also variable declaration.

 

[keikaku]

I'm not familiar with Eda playground, but your code is incomplete, it misses module header and end, also variable declaration.

thanks for the response. i added the header and the endmodule in addition to declaring the input. i am getting a different type of error now. i attached a screenshot.

 

[danadakk]

Variables — Documentation

Google "Verilog Cheatsheet", that should help.


Regards, Dana.

 

[dpaul]

you are right, it should be "trivial." but if i knew how to do it i would not be asking this question here. while i do see there are conversion sites, they do not explain the process.

You still did not answer the fundamental question on the number of clock cycles, which is important to determine the final Verilog code!
Hence I did not give out the solution. Nevertheless we keep this for the future!

You have shown us an EDA playground screenshot with just 3 lines of code and nothing more..............
For this I conclude that first of all you need to use a good Verilog book or a good online tutorial, learn at least the basics and then come back here.