there are three phases in one cycle.
When CLK1 is high, comparator is in the reset mode, which forces node a and b to be equal.
Next, when both CLK1 and CLK2 are low, M3 and M4 start to regenerate.
When CLK1 is low and CLK2 is high, transistors M3, M4, M7, M8 form two back to back inverters that cause voltage at node a and b to grow exponentially in the opposite directions.
The S-R latch part is used to store the output after the third phase and remains in this state in the next reset mode.