the_falcon
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I would like to know the detailed operation of the comparator schematic (Fig. 2) in the attached article.
... I meant to ask the guidance regarding the actual working operation of the comparator alone in terms of its each sections' part(diff. amplifier, SR latch and flipflop) in the working of the comparator. i am getting kinda confused with it ...
there are three phases in one cycle.
When CLK1 is high, comparator is in the reset mode, which forces node a and b to be equal.
Next, when both CLK1 and CLK2 are low, M3 and M4 start to regenerate.
When CLK1 is low and CLK2 is high, transistors M3, M4, M7, M8 form two back to back inverters that cause voltage at node a and b to grow exponentially in the opposite directions.
The S-R latch part is used to store the output after the third phase and remains in this state in the next reset mode.
Yes, I think so.so am i right that both the NMOSs M5 and M6 just the switches set to realize for clk2
M12 sources twice the current of M1 or M2. So I think its purpose is the initialization of the M3...M6 FF to its quiescent state, e.g. to a "0" start state. A connection to M3 then would initiate the "1" start state.... why the current source is connected to the M4 side of the flip flop section of the diagram
Is there any way for me to get some gain from the differential input stage M1 and M2 though I dont have any load connected to it.
I am getting confused with this factor as a comparator, the differential amplifier is supposed to have some gain to reduce the offset voltage of the comparator. I will attach the relevant technical paper with this message
i dont get any gain at all if i connect the circuit in that configuration with all the mentioned dimensions and also with the same bias current they mentioned. could you have any clue as why i am not able to get it. by the way, i am using 65 nm technology