explain transistor sizes before starts a layout

if transistor size and details are given as:-

pch_18
w=10u
l=2u
fingers=4
simM=2
total=8

what does this implies...plz help..

thx

Hi,
If I'm not mistaken, the specs. mean:
pch_18 -> p-type transistor model name (0.18um technology)
w=10u -> the transistor poly gate width (NOT transistor width)
l=2u -> the transistor poly gate length
fingers=4 -> the number of gate fingers
total=8 -> total length: fingers X l

In the picture, there are 2 fingers, with w of 0.45um & l of 2.3um giving total of 4.6um.

Best regards.

A small addition to what cop02ia already explained.
w in this case refers to the width per finger = 10u
"simM" -- refers to the no. of multipliers.
So, "total" = no.of. fingers X no. of multipliers = 4 X 2 = 8
So, the total width W (and not length "L") will be 10u X 8 = 80u

With fingers, you can have S/D sharing but you cannot do that with multipliers.
Hope it helps!

in the sentence:

In the picture, there are 2 fingers, with w of 0.45um & l of 2.3um giving total of 4.6um.

I think there is something wrong

the l (length) is the distance from S to D is 0.45um and W (width) is 2.3um.

Hi,
Nothing wrong with the picture.
I just wrote them according to the PDK that was used.

In THIS layout picture, the PDK used refers to the transistor poly gate width (NOT transistor width) & similarly with the length. It depends on who wrote the PDK (I have a PDK from a different foundry referring to transistor dimensions as well).

In layout designs, usually creating instances have specs. for fingers, their lengths (or transistor width) & the total length (or width, whichever). I thought 'total' was referring to 8um ( I've never seen any PDK referring to total = finger X m, yet, but you learn something new everyday ).

In schematic, multiplier m value is given but not in layout (I'm referring to Cadence tools btw - m is the default name for multiplier, if you check the .cdsenv example file given by Cadence in the installation directory).

Best regards.