firsttimedesigning
Full Member level 1
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recently i am studying CMFB. i have attached file that has a circuit uses CMFB.
my question is that when Id3 and Id4 increase, why does that ouptut CM get lowered?
I think it's because that there is a set amount of current flowing into R1 and R2 from PMOS transistors. There is also a set amount of current flowing out of R1 and R2, namely Id3 + Id4. Since Id3 + Id4 increase, there is more current flowing out of R1 and R2. Therefore, the output CM level decreases. I am not sure if I am right..
One thing that i should add is Ve is the difference between Vout,cm and Vref.
Vref is connected to the negative input of the amplifier.
I also would like to know why does the feedback circuit forces Vout,cm to be equal to Vref?
my question is that when Id3 and Id4 increase, why does that ouptut CM get lowered?
I think it's because that there is a set amount of current flowing into R1 and R2 from PMOS transistors. There is also a set amount of current flowing out of R1 and R2, namely Id3 + Id4. Since Id3 + Id4 increase, there is more current flowing out of R1 and R2. Therefore, the output CM level decreases. I am not sure if I am right..
One thing that i should add is Ve is the difference between Vout,cm and Vref.
Vref is connected to the negative input of the amplifier.
I also would like to know why does the feedback circuit forces Vout,cm to be equal to Vref?