expecting 'endmodule', found 'else'

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Abhisek hota

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Code Verilog - [expand]
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module ram_mem(din,add,rst,clk,en,rw,dout);
input [3:0]din;
input [5:0]add;
input rst,clk,en,rw;
output reg [3:0]dout;
reg [3:0]mem[0:63];
 
always@(clk)
begin
 
if(en)
    begin
        always@(posedge clk or negedge rst)
            begin
                if(rw)
                    mem[add]<=din;
                else
                    dout<=mem[add];
            end
    end
 
else
    begin
        always@(negedge clk or negedge rst)
            begin
                if(rw)
                    mem[add]<=din;
                else
                    dout<=mem[add];
            end
    end
    
end
 
endmodule
 
Last edited by a moderator:

Unpaired begin end statements, just count it and correct according to the intended program function.

Looks like you have pasted some code unintentionally twice, alos the surrounding always @(clk) makes no sense. I guess you wanted something like below.

By the way, using proper indentation can help you to read your own text.

Code Verilog - [expand]
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if(en)
begin
  always@(posedge clk or negedge rst)
  begin
    if(rw)
      mem[add]<=din;
    else
      dout<=mem[add];
  end
end
 


If (en) begin
always @ (posedge clk or negedge rst)
...
end


This isn't legal Verilog. It would only be legal if en was a static value at compile time, i.e a parameter or constant (selective compile based on a constant), but not using an input.

I think the OP doesn't know how to write the simplest behavioral description of a flip-flop:
Code Verilog - [expand]
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// simplest FF
always @ (posedge clk)
  q <= d;
// simple FF with async reset
always @ (posedge clk or negedge rst)
  if (!rst) q <= 0;
  else      q <= d;
 
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