I'm a college of jusik, who made an article on this forum.
He asked about DRC error "Every well must have at least one well tap"
I want to ask you about our problem more precisely.
1) First, we tried using NW(N-well) layer to make a GDPMOS(Ground-Vdd PMOS). During DRC, the error 'Every well must have at least one well tap' occurred.
However, I already made a n+ diffusion, whose layer name is 'NACT' in the design rule I have.
2) I didn't use instance to make body tap. I just hard copied a NMOS(which is specially made for ESD protection devices) from other file(this doesn't have macro) and changed all of the layers' properties to make PMOS. <- Can this make a problem?
3) Although the DRC of this GDPMOS failed, when I use this GDPMOS in other schematics or layouts as 'instance', there was no DRC or LVS error!
4) When I made a GGNMOS(Gate-Grounded NMOS), there was no error with PACT(p+). DRC and LVS was successful for GGNMOS.